Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2332
Datasheet
18.7.190 Debug Capability ID Register (DCID)—Offset 8480h
The Debug Capability ID Register links the USB Debug Capability into the xHCI list of 
Extended Capabilities and defines its basic capabilities. This register is modified and 
maintained by BIOS.
Access Method
Default: 0005000Ah
28:21
00h
RO
Rsvd4: 
Reserved.
Power Well: 
Core
20
0b
RO
SMI on Host System Error (SMIHSE): 
Reserved.
Power Well: 
SUS
19:17
0h
RO
Rsvd3: 
Reserved.
Power Well: 
Core
16
0b
RO
SMI on Event Interrupt (SMIEI): 
Reserved.
Power Well: 
SUS
15
0b
RW
SMI on BAR Enable (SMIBARE): 
Reserved.
Power Well: 
SUS
14
0b
RW
SMI on PCI Command Enable (SMIPCICE): 
Reserved.
Power Well: 
SUS
13
0b
RW
SMI on OS Ownership Enable (SMIOSOE): 
Reserved.
Power Well: 
SUS
12:5
00h
RO
Rsvd2: 
Reserved.
Power Well: 
Core
4
0b
RW
SMI on Host System Error Enable (SMIHSEE): 
Reserved.
Power Well: 
SUS
3:1
0h
RO
Rsvd1: 
Reserved.
Power Well: 
Core
0
0b
RW
USB SMI Enable (USBSMIE): 
Reserved.
Power Well: 
SUS
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h