Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2334
Datasheet
18.7.192 Debug Capability Event Ring Segment Table Size Register 
(DCERSTSZ)—Offset 8488h
The Debug Capability Event Ring Segment Table Size Register defines the number of 
segments supported by the Debug Capability Event Ring Segment Table.
Access Method
Default: 00000000h
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:16
00h
RW
Reserved (RSVD): 
Reserved.
Power Well: 
Core
15:8
00h
RW
Doorbell Target (DBTGT): 
This field defines the target of the doorbell reference. The 
table below defines the Debug Capability notification that is generated by ringing the 
doorbell. 
0 = Data EP 1 OUT Enqueue Pointer Update 
1 = Data EP 1 IN Enqueue Pointer Update 
2:255 = Reserved 
This field returns '0' when read and the value should be treated as undefined by 
software.
Power Well: 
Core
7:0
00h
RW
Reserved (RSVD_1): 
Reserved.
Power Well: 
Core
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
Offset: 
MBAR Type: 
PCI Configuration Register (Size: 64 bits)
MBAR Reference: 
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
ERST
S
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:16
0000h
RW
Reserved (RSVD): 
Reserved.
Power Well: 
Core
15:0
0000h
RW
Event Ring Segment Table Size (ERSTS): 
This field identifies the number of valid 
Event Ring Segment Table entries in the Event Ring Segment Table pointed to by the 
Debug Capability Event Ring Segment Table Base Address
 register. The maximum value 
supported by an xHC implementation for this register is defined by the DCERST Max 
field in the DCID register. See the xHCI USB specification for more information.  
Software shall initialize this register before setting the Debug Capability Enable field in 
the DCCTRL register to '1'.
Power Well: 
Core