Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2336

Datasheet

The Debug Capability Control Register is used to manage the Debug Capability.

Default: 00000000h

63:4

000000000

000000h

RW

This field defines the high order bits of the 64-bit address of 

the current Debug Capability Event Ring Dequeue Pointer.  

Software shall initialize this register before setting the Debug Capability Enable field in 

the DCCTRL register to '1'.

Core

3

0b

RW

Reserved.

Core

2:0

0h

RW

This field may be used by the xHC to 

accelerate checking the Event Ring full condition. This field is written with the low order 

3 bits of the offset of the ERST entry which defines the Event Ring segment that the 

Event Ring Dequeue Pointer resides in.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DC

E

DADD

R

DMBS

RSVD

DRC

HI

T

HO

T

LSE

DC

R

31

0b

RW

Setting this bit to a 1 enables xHCI USB Debug 

Capability operation. This bit is a 0 if the USB Debug Capability is disabled. Clearing this 

bit releases the Root Hub port assigned to the Debug Capability, and terminates any 

Debug Capability Transfer or Event Ring activity.

Core

30:24

00h

RO

This field reports the USB device address assigned to the 

Debug Device during the enumeration process. This field is valid when the DbC Run bit 

is 1.

Core

23:16

00h

RO

This field identifies the maximum burst size 

supported by the bulk endpoints of this DbC implementation. LPT-LP USB Debug Device 

does not support bursting.

Core