Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2337
18.7.196 Debug Capability Status Register (DCST)—Offset 84A4h
The Debug Capability Status Register reports capability related status information to
software.
Access Method
Default: 00000000h
15:5
000h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
4
0b
RW/C
DbC Run Change (DRC):
This bit shall be set to '1' when DCR bit is cleared to '0', i.e.
by any DbC Port State transition that exits the DbC-Configured state. While this bit is 1
the Debug Capability Doorbell Register (DCDB) is disabled. Software shall clear this bit
to re-enable the DCDB.
Power Well:
Core
3
0b
RW/S
Halt IN TR (HIT):
While this bit is 1 the Debug Capability shall generate STALL TPs for
all OUT DPs received for the IN TR. The Debug Capability shall clear this bit when a
ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is valid
only when the Debug Capability is in Run Mode (DCR = 1). When not in Run Mode, this
field shall return 0 when read, and writes will have no effect. Refer to the xHCI USB
specification for more information.
Power Well:
Core
2
0b
RW/S
Halt OUT TR (HOT):
While this bit is 1 the Debug Capability shall generate STALL TPs
for all IN TPs received for the OUT TR. The Debug Capability shall clear this bit when a
ClearFeature(ENDPOINT_HALT) request is received for the endpoint. This field is valid
only when the Debug Capability is in Run Mode (DCR = 1). When not in Run Mode, this
field shall return 0 when read, and writes will have no effect. Refer to the xHCI USB
specification for more information.
Power Well:
Core
1
0b
RW
Link Status Event Enable (LSE):
Setting this bit to a 1 enables the Debug Capability
to generate Port Status Change Events due to the Port Link Status Change bit
transitioning from a 0 to a 1. Refer to the xHCI USB specification for more information.
Power Well:
Core
0
0b
RO
DbC Run (DCR):
When 0, Debug Device is not in the Configured state. When 1, Debug
Device is in the Configured state and bulk Data pipe transactions are accepted by Debug
Capability and routed to the IN and OUT Transfer Rings. A 0 to 1 transition of the Port
Reset
(DCPORTSC:PR) bit will clear this bit to 0.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DPNUM
RSVD
ERNE