Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2338

Datasheet

The fields of the Debug Capability PORTSC Register are defined below and provide 

information about the state of the Root Hub port that is assigned to the Debug 

Capability. Note that the fields in this register function differently than those in a 

normal Port Status and Control Register (described in section 5.4.8) because the Root 

Hub port assigned to the Debug Capability is acting as an Upstream Facing Port, not a 

Downstream Facing Port.

Default: 00000000h

31:24

00h

RO

This field provides the ID of the Root Hub port that 

the Debug Capability has been automatically attached to. The value is '0' when the 

Debug Capability is not attached to a Root Hub port.

Core

23:1

000000h

RO

Reserved.

Core

0

0b

RO

When '1', this field indicates that the Debug 

Capability Event Ring has a Transfer Event on it. It is automatically cleared to '0' by the 

xHC when the Debug Capability Event Ring is empty, i.e. the Debug Capability Enqueue 

Pointer is equal to the Debug Capability Event Ring Dequeue Pointer register.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSV

D

CE

C

PL

C

PRC

RSV

D

_1

CS

C

RSV

D

_2

PS

PD

RSV

D

_3

PL

S

PR

RSV

D

_4

PED

CC

S

31:24

00h

RO

Reserved.

Core

23

0b

RW/C

This flag indicates that the port failed to configure 

its link partner. 
•

0  =  No  change 

•

1 = Port Config Error detected 

Software shall clear this bit by writing a '1' to it.

Core