Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2340

Datasheet

Default: 0000000000000000h

4

0b

RO

Port Reset (PR): 
•

'1' = Port is in Reset 

•

'0' = Port is not in Reset 

This bit is set to '1' when the bus reset sequence as defined in the USB Specification is 

detected on the Root Hub port assigned to the Debug capability. It is cleared when the 

bus reset sequence is completed by the Debug Host, and the DbC shall transition to the 

USB Default state. A '0' to '1' transition of this bit shall clear DCPORTSC PED ('0'). This 

field is '0' if DCE or CCS are '0'.

Core

3:2

0h

RO

Reserved.

Core

1

0b

RW

Port Enabled/Disabled (PED): 
•

'1' = Enabled. 

•

'0'  =  Disabled. 

This flag shall be set to '1' by a '0' to '1' transition of CCS or a '1' to '0' transition of the 

PR. When PED transitions from '1' to '0' due to the assertion of PR, the port's link shall 

transition to the Rx.Detect state. This flag may be used by software to enable or disable 

the operation of the Root Hub port assigned to the Debug Capability. The Debug 

Capability Root Hub port operation may be disabled by a fault condition (disconnect 

event or other fault condition, e.g. a LTSSM Polling substate timeout, tPortConfiguration 

timeout error, etc.), the assertion of DCPORTSC PR, or by software. 
•

0 = Debug Capability Root Hub port is disabled. 

•

1 = Debug Capability Root Hub port is enabled. 

When the port is disabled (PED = '0') the port's link shall enter the SS.Disabled state 

and remain there until PED is reasserted ('1') or DCE is negated ('0'). Note that the Root 

Hub port is remains mapped to Debug Capability while PED = '0'. While PED = '0' the 

Debug Capability will appear to be disconnected to the Debug Host. Note: This bit is not 

affected by PORTSC PR bit transitions. This field is '0' if DCE or CCS are '0'.

Core

0

0b

RO

Current Connect Status (CCS): 
•

'1' = A Root Hub port is connected to a Debug Host and assigned to the Debug 

Capability. 

•

'0' = No Debug Host is present. 

This value reflects the current state of the port, and may not correspond to the value 

reported by the Connect Status Change (CSC) field in the Port Status Change Event that 

was generated by a '0' to '1' transition of this bit. This flag is '0' if Debug Capability 

Enable (DCE) is '0'.

Core

Memory Mapped I/O Register

(Size: 64 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h