Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2341
18.7.199 Debug Capability Device Descriptor Info Register 1 (DCDDI1)—
Offset 84B8h
The Debug Capability Device Descriptor Register 1 identifies the Device Protocol and
Vendor ID values that shall be reported by DbC in its Device Descriptor when it is
enumerated by a Debug Host. Refer to section 9.6.1, Table 9-8 in the USB3 spec. This
register shall be initialized before enabling the DbC (DCE = '1').
Access Method
Default: 00000000h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DC
CPR
RSV
D
Bit
Range
Default &
Access
Field Name (ID): Description
63:4
000000000
000000h
RW
Debug Capability Context Pointer Register (DCCPR):
This field defines the high
order bits of the start address of the Debug Capability Context data structure associated
with the Debug Capability. Software shall initialize this register before setting the Debug
Capability Enable bit in the Debug Capability Control Register to '1'.
Power Well:
Core
3:0
0h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID
R
SVD
D
B
CP
R
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RW
Vendor ID (VID):
This field is presented by the Debug Device in the USB Device
Descriptor idVendor field.
Power Well:
Core
15:8
00h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core