Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2343
18.7.202 Debug Device Control ODMA (DBGDEV_CTRL_ODMA_REG)—
Offset 8538h
This register contains a number of fields that provide a specific level of configurability
for the OUT DMA that is part of Debug Device logic. This configurability is above and
beyond that defined in the xHCI specification.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
MP
F
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
000000h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
7:0
00h
RW
Max Power Field (MPF):
This field will be used by USB Debug Device to report
maximum power consumption when the device is fully operational. This value is
returned by bMaxPower field in response to Configuration Descriptor read from the
debug device. Note: bU1DevExitLat and bU2DevExitLat fields returned in BOS
Descriptor read will be taken from the corresponding fields from the Host Controller
space.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
E
N
_A
CK
_
FCA
RSV
D
_1
EN_A
CK
_
FIFO
_
ICA
RSV
D
_2
CL_OWN_C
S
RET_OD_ACK_CR
RSV
D
_3
RET_O
D
C
F_S
M_
IS
RE
T_ODRF_S
M_
IS
RE
T_ODRDF_S
M
_
IS
RSV
D
_4
Bit
Range
Default &
Access
Field Name (ID): Description
31:19
0000h
RO
Reserved (RSVD):
Reserved.
Power Well:
Core
18
0b
RW
Enable ACK FIFO credit accounting (EN_ACK_FCA):
Setting this field will enable
ACK FIFO credit accounting. ODMA will ensure that ample room exists in the ACK FIFO
for expected device responses prior to initiating a given DP
Power Well:
Core