Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2346
Datasheet
18.8.1
Vendor ID and Device ID (VID_DID)—Offset 0h
Access Method
Default: 00008086h
18.8.2
Command and Device Status (CMD_STS)—Offset 4h
Access Method
Default: 02900000h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0
RSV
D
VID_0
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Reserved (RSVD):
Reserved.
15:0
8086h
RO
Vendor ID (VID_0):
16-bit field which indicates company vendor as Intel.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DPE
_
0
SS
E
_
0
RMA
_
0
RT
A
_
0
ST
A
_
0
DE
V
T
_
0
MDPED
_
0
FBC
A
P_
0
UD
F_
0
CLK
C
A
P_0
CA
PLIS
T_
0
INTRST
S_
0
R
SVD
INTRDIS_
0
FBE
_
0
S
E
RRE
N_
0
WCC_
0
PE
R
_
0
VG
AP
S
_
0
PM
WE_
0
SC
E
_
0
BME
_
0
MSE
_
0
IO
SE
_0
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RWC
Detected Parity Error (DPE_0):
This bit is set whenever a parity error is seen on the
internal interface to the USB2 host controller, regardless of the setting of bit 6 or bit 8 in
the Command register or any other conditions. Software clears this bit by writing a '1' to
this bit location.
Power Well:
Core
30
0b
RWC
Signaled System Error (SSE_0):
This bit is set whenever it signals SERR#
(internally). The SERR_EN bit (bit 8 in the Command Register) must be 1 for this bit to
be set. The following conditions can cause the generation of SERR#: a parity error is
seen on address, command, or data (if the data was targeting the EHC) on the internal
interface to the USB2 host controller due to a parity error on the system interface and
bit 6 of the Command register is set to 1. An EHC-initiated memory read results in a
completion packet with a status other than successful on the system interface (if SERR
on Aborts Enable is also set) Software clears this bit by writing a '1' to this bit location.
Power Well:
Core