Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2353
18.8.8
Interrupt Line and Interrupt Pin and Reserved
(ILINE_IPIN_RSVD)—Offset 3Ch
Access Method
Default: 00000000h
18.8.9
PCI Power Management Capability ID and Next Item Pointer #1
and PM Capabilities (PM_CID_NEXT_CAP)—Offset 50h
PCI Power Management Capabilities ID Next Item Pointer #1 Power Management
Capabilities
Access Method
Default: C9C35801h
7:0
50h
RO
Capabilities Pointer (CAP_PTR_0):
This register points to the starting offset of the
USB2 capabilities ranges.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
IP
IN
_
0
ILINE_0
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Reserved (RSVD):
Reserved.
15:8
00h
RO
Interrupt Pin (IPIN_0):
Bits 3:0 reflect the value programmed in the interrupt pin
registers in chipset configuration space. Bits 7:4 are hardwired to 0000b. NOTE: As a
single function device, only INTA# may be used while the other three interrupt lines
have no meaning. (refer to PCI 3.0 spec section 2.2.6 Interrupt Pins)
Power Well:
Core
7:0
00h
RW
Interrupt line (ILINE_0):
This data is not used by the SOC. It is used as a scratchpad
register to communicate to software the interrupt line that the interrupt pin is connected
to. Reset: core well and D3-to-D0.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 32 bits)
Offset: