Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2354
Datasheet
31
28
24
20
16
12
8
4
0
1 1 0 0 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1
RSVD
D2SUP_0
D1SUP_0
AU
XCUR
_0
DS
I_0
RSVD
PM
E
C
LK
_
0
VERS
_0
PM_NE
X
T_0
PM_CI
D
_0
Bit
Range
Default &
Access
Field Name (ID): Description
31:27
11001b
RO
Reserved (RSVD):
Reserved.
26
0b
RO
D2_Support (D2SUP_0):
The D2 state is not supported. Reset: core well, but not D3-
to-D0.
Power Well:
Core
25
0b
RO
D1_Support (D1SUP_0):
The D1 state is not supported. Reset: core well, but not D3-
to-D0.
Power Well:
Core
24:22
111b
RW/L
Aux_Current (AUXCUR_0):
The USB2 SIP EHC reports 375mA maximum Suspend
well current required when in the D3cold state. This value can be written by BIOS when
a more accurate value is known.
Power Well:
Core
21
0b
RO
DSI (DSI_0):
The Intel EHC reports 0, indicating that no device-specific initialization is
required. Reset: core well, but not D3-to-D0.
Power Well:
Core
20
0b
RO
Reserved (RSVD):
Reserved.
19
0b
RO
PME Clock (PMECLK_0):
The Intel EHC reports 0, indicating that no PCI clock is
required to generate PME#. Reset: core well, but not D3-to-D0.
Power Well:
Core
18:16
011b
RW/L
Version (VERS_0):
Version: The Intel EHC reports 011, indicating that it complies with
Revision 1.21 of the PCI Power Management Specification. Note: As contigency plan, the
bit can be reverted by BIOS to 010b to support PCI PM Revision 1.1, by manipulating
the offset80h Access Control register's WRT_RDONLY bit.
Power Well:
Core
15:8
58h
RW/L
Next Item Pointer #1 (PM_NEXT_0):
This register defaults to 58h, which indicates
that the next capability registers begin at configuration offset 58h. This register is
writable when the WRT_RDONLY bit is set. This allows BIOS to effectively hide the
Debug Port capability registers, if necessary. This register should only be written during
system initialization before the plug-and-play software has enabled any master-initiated
traffic. Values of 58h implies Debug Port and FLR capabilities visible 98h implies Debug
Port invisible, next capability is FLR 00h implies that both Debug port and FLR capability
are hidden Note that this value is never expected to be programmed. Reset: core well,
but not D3-to-D0
Power Well:
Core