Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2359
18.8.14
USB2 Legacy Support Extended Capability (ULSEC)—Offset 68h
Access Method
Default: 00000001h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RSV
D
HC
OSO
S
_0
RSV
D
HC
B
IOS
_0
Nx
tE
HC
IC
ap
P_
0
Ca
p
ID_
0
Bit
Range
Default &
Access
Field Name (ID): Description
31:25
0000000b
RO
Reserved (RSVD):
Reserved.
24
0b
RW
HC OS Owned Semaphore (HCOSOS_0):
System software sets this bit to request
ownership of the EHCI controller. Ownership is obtained when this bit reads as 1 and the
HC BIOS Owned Semaphore bit reads as clear. This register is implemented in the
Suspend Well. This register is only reset by the resume power well going low. It is not
reset by the core power well going low or by a D3-to-D0 state transition.
Power Well:
Resume
23:17
0000000b
RO
Reserved (RSVD):
Reserved.
16
0b
RW
HC BIOS Owned Semaphore (HCBIOS_0):
The BIOS sets this bit to establish
ownership of the EHCI controller. System BIOS will clear this bit in response to a request
for ownership of the EHCI controller by system software. This register is implemented in
the Suspend Well. This register is only reset by the resume power well going low. It is
not reset by the core power well going low or by a D3-to-D0 state transition.
Power Well:
Resume
15:8
00h
RO
Next EHCI Capability Pointer (NxtEHCICapP_0):
A value of 00h indicates that
there are no EHCI Extended Capability structures in this device. This register is
implemented in the Suspend Well. This register is only reset by the resume power well
going low. It is not reset by the core power well going low or by a D3-to-D0 state
transition.
Power Well:
Resume
7:0
01h
RO
Capability ID (CapID_0):
A value of 01h indicates that this EHCI Extended Capability
is the Legacy Support Capability. This register is implemented in the Suspend Well. This
register is only reset by the resume power well going low. It is not reset by the core
power well going low or by a D3-to-D0 state transition.
Power Well:
Resume