Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2360
Datasheet
18.8.15
USB2 Legacy Support Control/Status (ULSCS)—Offset 6Ch
Access Method
Default: 00000000h
Type: 
PCI Configuration Register
(Size: 32 bits)
Offset: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SMIon
B
AR_0
SM
IonPC
ICom_0
S
M
IonOS
S
C
_
0
RSV
D
SMIonA
A_0
SMIo
nHS
E
_0
SM
Ion
FL
R
_0
SMIonPC
D
_0
SM
Ion
U
E
_
0
SMIoU
S
BC
_0
SMIonBA
R
E_0
S
M
Io
nP
CICE
_0
SMI
on
O
S
S
OE
_0
RSV
D
SM
Ion
A
AE
_0
SMIonH
SE
E_0
SMIonFL
R
E_0
SMIonPC
E
_0
S
M
IonUSBE
E
_0
SMIo
nU
SBC
E
_0
Bit 
Range
Default & 
Access
Field Name (ID): Description
31
0b
RWC
SMI on BAR (SMIonBAR_0): 
This bit is set to '1' whenever the Base Address Register 
(BAR) is written. This register is only reset by the resume power well going low. It is not 
reset by the core power well going low or by a D3-to-D0 state transition.
Power Well: 
Resume
30
0b
RWC
SMI on PCI Command (SMIonPCICom_0): 
This bit is set to '1' whenever the PCI 
Command Register is written. This register is only reset by the resume power well going 
low. It is not reset by the core power well going low or by a D3-to-D0 state transition.
Power Well: 
Resume
29
0b
RWC
SMI on OS Ownership Change (SMIonOSSC_0): 
This bit is set to '1' whenever the 
HC OS Owned Semaphore bit in the USB2 Legacy Support Extended Capability register 
transitions from 1 to a 0 or 0 to a 1. This register is only reset by the resume power well 
going low. It is not reset by the core power well going low or by a D3-to-D0 state 
transition.
Power Well: 
Resume
28:22
00h
RO
Reserved (RSVD): 
Reserved.
21
0b
RO
SMI on Async Advance (SMIonAA_0): 
Shadow bit of the Interrupt on Async Advance 
bit in the USB2STS register. To clear this bit system software must write a one to the 
Interrupt on Async Advance bit in the USB2STS register. This register is only reset by 
the resume power well going low. It is not reset by the core power well going low or by 
a D3-to-D0 state transition.
Power Well: 
Resume
20
0b
RO
SMI on Host System Error (SMIonHSE_0): 
Shadow bit of Host System Error bit in 
the USB2STS. To clear this bit system software must write a one to the Host System 
Error bit in the USB2STS register. This register is only reset by the resume power well 
going low. It is not reset by the core power well going low or by a D3-to-D0 state 
transition.
Power Well: 
Resume