Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2361
19
0b
RO
SMI on Frame List Rollover (SMIonFLR_0):
Shadow bit of Frame List Rollover bit in
the USB2STS register. To clear this bit system software must write a one to the Frame
List Rollover bit in the USB2STS register. This register is only reset by the resume power
well going low. It is not reset by the core power well going low or by a D3-to-D0 state
transition.
Power Well:
Resume
18
0b
RO
SMI on Port Change Detect (SMIonPCD_0):
Shadow bit of Port Change Detect bit in
the USB2STS register. To clear this bit system software must write a one to the Port
Change Detect bit in the USB2STS register. This register is only reset by the resume
power well going low. It is not reset by the core power well going low or by a D3-to-D0
state transition.
Power Well:
Resume
17
0b
RO
SMI on USB Error (SMIonUE_0):
Shadow bit of USB Error Interrupt (USBERRINT) bit
in the USB2STS register. To clear this bit system software must write a one to the USB
Error Interrupt bit in the USB2STS register. This register is only reset by the resume
power well going low. It is not reset by the core power well going low or by a D3-to-D0
state transition.
Power Well:
Resume
16
0b
RO
SMI on USB Complete (SMIoUSBC_0):
Shadow bit of USB Interrupt (USBINT) bit in
the USB2STS register. To clear this bit system software must write a one to the USB
Interrupt bit in the USB2STS register. This register is only reset by the resume power
well going low. It is not reset by the core power well going low or by a D3-to-D0 state
transition.
Power Well:
Resume
15
0b
RW
SMI on BAR Enable (SMIonBARE_0):
When this bit is '1' and SMIonBAR_0 is '1',
then the host controller will issue an SMI. This register is only reset by the resume
power well going low. It is not reset by the core power well going low or by a D3-to-D0
state transition.
Power Well:
Resume
14
0b
RW
SMI on PCI Command Enable (SMIonPCICE_0):
When this bit is '1' and SMI on PCI
Command is '1', then the host controller will issue an SMI. This register is only reset by
the resume power well going low. It is not reset by the core power well going low or by
a D3-to-D0 state transition.
Power Well:
Resume
13
0b
RW
SMI on OS Ownership Enable (SMIonOSSOE_0):
When this bit is a one AND the OS
Ownership Change bit is one, the host controller will issue an SMI. This register is only
reset by the resume power well going low. It is not reset by the core power well going
low or by a D3-to-D0 state transition.
Power Well:
Resume
12:6
00h
RO
Reserved (RSVD):
Reserved.
5
0b
RW
SMI on Async Advance Enable (SMIonAAE_0):
When this bit is a one, and the SMI
on Async Advance bit is a one, the host controller will issue an SMI immediately. This
register is only reset by the resume power well going low. It is not reset by the core
power well going low or by a D3-to-D0 state transition.
Power Well:
Resume
Bit
Range
Default &
Access
Field Name (ID): Description