Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2362
Datasheet
4
0b
RW
SMI on Host System Error Enable (SMIonHSEE_0):
When this bit is a one, and the
SMI on Host System Error is a one, the host controller will issue an SMI. This register is
only reset by the resume power well going low. It is not reset by the core power well
going low or by a D3-to-D0 state transition.
Power Well:
Resume
3
0b
RW
SMI on Frame List Rollover Enable (SMIonFLRE_0):
When this bit is a one, and the
SMI on Frame List Rollover bit is a one, the host controller will issue an SMI. This
register is only reset by the resume power well going low. It is not reset by the core
power well going low or by a D3-to-D0 state transition.
Power Well:
Resume
2
0b
RW
SMI on Port Change Enable (SMIonPCE_0):
When this bit is a one, and the SMI on
Port Change Detect bit is a one, the host controller will issue an SMI. This register is
only reset by the resume power well going low. It is not reset by the core power well
going low or by a D3-to-D0 state transition.
Power Well:
Resume
1
0b
RW
SMI on USB Error Enable (SMIonUSBEE_0):
When this bit is a one, and the SMI on
USB Error bit is a one, the host controller will issue an SMI immediately. This register is
only reset by the resume power well going low. It is not reset by the core power well
going low or by a D3-to-D0 state transition.
Power Well:
Resume
0
0b
RW
SMI on USB Complete Enable (SMIonUSBCE_0):
When this bit is a one, and the
SMI on USB Complete bit is a one, the host controller will issue an SMI immediately.
This register is only reset by the resume power well going low. It is not reset by the core
power well going low or by a D3-to-D0 state transition.
Power Well:
Resume
Bit
Range
Default &
Access
Field Name (ID): Description