Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2364

Datasheet

16

0b

RWC

This bit is set to '1' whenever HCRESET 

transitions to '1'. This register is implemented in the Suspend Well. This register is only 

reset by the resume power well going low. It is not reset by the core power well going 

low or by a D3-to-D0 state transition

Resume

15:6

000h

RW

When any of these bits are '1' and the 

corresponding SMI on PortOwner bits are '1', then the host controller will issue an SMI. 

Unused ports should have their corresponding bits cleared. This register is only reset by 

the resume power well going low. It is not reset by the core power well going low or by 

a D3-to-D0 state transition

Resume

5

0b

RW

When this bit is '1' and SMI on PMSCR 

is '1', then the host controller will issue an SMI. This register is only reset by the resume 

power well going low. It is not reset by the core power well going low or by a D3-to-D0 

state transition

Resume

4

0b

RW

When this bit is '1 and SMI on Async is '1' 

, then the host controller will issue an SMI. This register is implemented in the Suspend 

Well. This register is only reset by the resume power well going low. It is not reset by 

the core power well going low or by a D3-to-D0 state transition

Resume

3

0b

RW

When this bit is '1 and SMI on 

Periodic is '1', then the host controller will issue an SMI. This register is implemented in 

the Suspend Well. This register is only reset by the resume power well going low. It is 

not reset by the core power well going low or by a D3-to-D0 state transition

Resume

2

0b

RW

When this bit is '1' and SMI on CF is '1', then the 

host controller will issue an SMI. This register is implemented in the Suspend Well. This 

register is only reset by the resume power well going low. It is not reset by the core 

power well going low or by a D3-to-D0 state transition

Resume

1

0b

RW

When this bit is a '1' and SMI on 

HCHalted is '1', then the host controller will issue an SMI. This register is implemented 

in the Suspend Well. This register is only reset by the resume power well going low. It is 

not reset by the core power well going low or by a D3-to-D0 state transition

Resume

0

0b

RW

When this bit is a '1' and SMI on 

HCHalted is '1', then the host controller will issue an SMI. This register is implemented 

in the Suspend Well. This register is only reset by the resume power well going low. It is 

not reset by the core power well going low or by a D3-to-D0 state transition

Resume