Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2365
18.8.17
OverCurrent Mapping (OCMAP)—Offset 74h
Access Method
Default: C0300C03h
18.8.18
EHC Suspend Well Configuration and RMH Wake Control
(EHCSUSCFGRMHWC)—Offset 7Ch
Access Method
Default: 0000408Ch
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1
OC
MAP
D
_0
OC
MAP
C
_0
OC
MAP
B
_0
OC
MAP
A
_0
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
C0h
RW
OC Mapping D (OCMAPD_0):
Each bit position maps OC4, for EHCI1 to a set of ports
as follows: The OC4 pin is ganged to the overcurrent signal of each port that has its
corresponding bit set. It is SW's responsibility to ensure that a given port's bit map is
set only for one OC pin.
Power Well:
Resume
23:16
30h
RW
OC Mapping C (OCMAPC_0):
OC Mapping C. Each bit position maps OC3, for EHCI1 to
a set of ports as follows: The OC3 pin is ganged to the overcurrent signal of each port
that has its corresponding bit set. It is SW's responsibility to ensure that a given port's
bit map is set only for one OC pin.
Power Well:
Resume
15:8
0Ch
RW
OC Mapping B (OCMAPB_0):
OC Mapping B. Each bit position maps OC2, for EHCI1 to
a set of ports as follows: The OC2 pin is ganged to the overcurrent signal of each port
that has its corresponding bit set. It is SW's responsibility to ensure that a given port's
bit map is set only for one OC pin.
Power Well:
Resume
7:0
03h
RW
OC Mapping A (OCMAPA_0):
OC Mapping A: Each bit position maps OC1, for EHCI1
to a set of ports as follows: The OC1 pin is ganged to the overcurrent signal of each port
that has its corresponding bit set. It is SW's responsibility to ensure that a given port's
bit map is set only for one OC pin.
Power Well:
Core
Type:
PCI Configuration Register
(Size: 32 bits)
Offset: