Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

Datasheet

2369

18.9

USB EHCI Memory Mapped IO Registers

Table 213. Summary of USB EHCI Memory Mapped I/O Registers—MBAR

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default Value

0–0h

“Capability Registers Length and HC Interface Version
Number (CAP_HCIV)—Offset 0h” on page 2370

01000020h

4–4h

“Host Controller Structural Parameters (HCSPARAMS)—Offset
4h” on page 2371

00200008h

8–Bh

“Host Controller Capability Parameters (HCCPARAMS)—Offset
8h” on page 2372

00036881h

20–23h

“USB2 Command Register (USB2CMD)—Offset 20h” on
page 2374

00080000h

24–27h

“USB2 Status (USB2STS)—Offset 24h” on page 2377

00001000h

28–2Bh

“USB2 Interrupt Enable (USB2INTR)—Offset 28h” on
page 2379

00000000h

2C–2Fh

“Frame Index (FRINDEX)—Offset 2Ch” on page 2380

00000000h

30–33h

“Control Data Structure Segment Register
(CTRLDSSEGMENT)—Offset 30h” on page 2381

00000000h

34–37h

“Periodic Frame List Base Address (PERIODICLISTBASE)—
Offset 34h” on page 2381

00000000h

38–3Bh

“Current Asynchronous List Address (ASYNCLISTADDR)—
Offset 38h” on page 2382

00000000h

60–63h

“Configure Flag Register (CONFIGFLAG)—Offset 60h” on
page 2383

00000000h

64–67h

“Port Status and Control (PORTSC1)—Offset 64h” on
page 2384

00003000h

68–6Bh

“Port Status and Control (PORTSC2)—Offset 68h” on
page 2388

00003000h

6C–6Fh

“Port Status and Control (PORTSC3)—Offset 6Ch” on
page 2393

00003000h

70–73h

“Port Status and Control (PORTSC4)—Offset 70h” on
page 2397

00003000h

74–77h

“Port Status and Control (PORTSC5)—Offset 74h” on
page 2402

00003000h

78–7Bh

“Port Status and Control (PORTSC6)—Offset 78h” on
page 2406

00003000h

7C–7Fh

“Port Status and Control (PORTSC7)—Offset 7Ch” on
page 2411

00003000h

80–83h

“Port Status and Control (PORTSC8)—Offset 80h” on
page 2415

00003000h

A0–A0h

“Debug Port Control/Status Register (DP_CTRLSTS)—Offset
A0h” on page 2420

00000000h