Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2372
Datasheet
18.9.3
Host Controller Capability Parameters (HCCPARAMS)—
Offset 8h
Access Method
Default: 00036881h
11:8
0h
RO
Number of Ports per Companion Controller (N_PCC_0): This field
indicates the number of ports supported per companion host controller. It is
used to indicate the port routing configuration to system software. Read-
Only. This register is only reset by the resume power well going low. It is not
reset by a D3-to-D0 state transition or HCRESET (Host Controller Reset)
indicates the number of ports supported per companion host controller. It is
used to indicate the port routing configuration to system software. Read-
Only. This register is only reset by the resume power well going low. It is not
reset by a D3-to-D0 state transition or HCRESET (Host Controller Reset)
Power Well: Core
7
0b
RO
Port Routing Rules (PRR_0): This field indicates the method used by this
implementation for how all ports are mapped to companion controllers. This
is hardwired to 0, indicating that the first N_PCC (=2) ports are routed to the
lowest numbered function companion host controller, the next N_PCC ports
are routed to the next lowest function companion controller, and so on
implementation for how all ports are mapped to companion controllers. This
is hardwired to 0, indicating that the first N_PCC (=2) ports are routed to the
lowest numbered function companion host controller, the next N_PCC ports
are routed to the next lowest function companion controller, and so on
Power Well: Resume
6:5
00b
RO
Reserved (RSVD): Reserved.
4
0b
RO
Reserved (RSVD): Reserved.
3:0
8h
RW
N_PORTS (NPORTS_0): This field specifies the number of physical
downstream ports implemented on this host controller. The value of this field
determines how many port registers are addressable in the Operational
Register Space. Valid values are in the range of 1H to FH. The default value
for the EHCI controller indicates 8 ports. BIOS may overwrite the default
value to properly describe the board or chip SKU . (please refer to RMH
Configuration Details in section 1.23.2). A zero in this field is undefined.
Integrated RMH - If USBr is disabled, this should be updated by BIOS to 2
such that the EHC reports 2ports to be default, port 0 assigned to the RMH
and port 1 assigned to the debug device. If USB-R is enabled, the number
reported should be updated to 3 by BIOS (port 2 will be assigned to USB-R in
this case) Legacy Mode - The default value for the EHCI controller indicates 8
ports. If USB-R support is enabled, BIOS should account for the additional
ports in calculating the value to write to this field.
downstream ports implemented on this host controller. The value of this field
determines how many port registers are addressable in the Operational
Register Space. Valid values are in the range of 1H to FH. The default value
for the EHCI controller indicates 8 ports. BIOS may overwrite the default
value to properly describe the board or chip SKU . (please refer to RMH
Configuration Details in section 1.23.2). A zero in this field is undefined.
Integrated RMH - If USBr is disabled, this should be updated by BIOS to 2
such that the EHC reports 2ports to be default, port 0 assigned to the RMH
and port 1 assigned to the debug device. If USB-R is enabled, the number
reported should be updated to 3 by BIOS (port 2 will be assigned to USB-R in
this case) Legacy Mode - The default value for the EHCI controller indicates 8
ports. If USB-R support is enabled, BIOS should account for the additional
ports in calculating the value to write to this field.
Power Well: Resume
Bit
Range
Default
& Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h