Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2376

Datasheet

4

0b

RW

Periodic Schedule Enable (PSE_0): This bit controls whether the host 
controller skips processing the Periodic Schedule. Values mean: 0b Do not 
process the Periodic Schedule 1b Use the PERIODICLISTBASE register to 
access the Periodic Schedule.

Power Well: Core

3:2

00b

RO

Frame List Size (FLS_0): This field is R/W only if Programmable Frame List 
Flag in the HCCPARAMS registers is set to a one. . This field specifies the size 
of the frame list. The size the frame list controls which bits in the Frame 
Index Register should be used for the Frame List Current index. Values 
mean:00b 1024 elements (4096 bytes) Default value; 01b 512 elements 
(2048 bytes); 10b 256 elements (1024 bytes) - for resource-constrained 
environments

Power Well: Core

1

0b

RW

Host Controller Reset (HCRESET_0): This control bit used by software to 
reset the host controller. The effects of this on Root Hub registers are similar 
to a Chip Hardware Reset. When software writes a one to this bit, the Host 
Controller resets its internal pipelines, timers, counters, state machines, etc. 
to their initial value. Any transaction currently in progress on USB is 
immediately terminated. A USB reset is not driven on downstream ports. 
Note: PCI Configuration registers and Host Controller Capability Registers are 
not affected by this reset. All operational registers, including port registers 
and port state machines are set to their initial values. Port ownership will be 
disowned by the host controller(s), with the side effects described in the 
EHCI spec. Software must reinitialize the host controller in order to return 
the host controller to an operational state. This bit is set to zero by the Host 
Controller when the reset process is complete. Software cannot terminate 
the reset process early by writing a zero to this register. Software should not 
set this bit to a one when the HCHalted bit in the USBSTS register is a zero. 
Attempting to reset an actively running host controller will result in 
undefined behavior. This reset must be used to leave EHCI port test modes.

Power Well: Core

0

0b

RW

Run/Stop (RS_0): 1=Run. 0=Stop. When set to a 1, the Host Controller 
proceeds with execution of the schedule. The Host Controller continues 
execution as long as this bit is set to a 1. When this bit is set to 0, the Host 
Controller completes the current and any actively pipelined transactions on 
the USB and then halts. The Host Controller must halt within 16 microframes 
after software clears the Run bit. The HC Halted bit in the status register 
indicates when the Host Controller has finished its pending pipelined 
transactions and has entered the stopped state. Software should not write a 
1 to this field unless the host controller is in the Halted state (i.e. HCHalted in 
the USBSTS register is a one). The following table explains how the different 
combinations of Run and Halted must be interpreted: Run/Stop Halted 
Interpretation 0 0 Valid- in the process of halting 0 1 Valid- halted 1 0 Valid- 
running 1 1 Invalid- the HCHalted bit clears immediately Memory read cycles 
initiated by the EHC that receive any status other than Successful will result 
in this bit being cleared (and also affect the Host Error bit).

Power Well: Core