Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2377
18.9.5
USB2 Status (USB2STS)—Offset 24h
Access Method
Default: 00001000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
ASS
_
0
PS
S_0
RECL_0
HCHAL
T
_0
RSVD
IAA_0
HSE_0
FL
R_
0
PC
D_0
USB
E
R
R
IN
T_
0
USB
INT_0
Bit
Range
Default
& Access
Field Name (ID): Description
31:16
0000h
RO
Reserved (RSVD): Reserved.
15
0b
RO
Asynchronous Schedule Status (ASS_0): This bit reports the current real
status of the Asynchronous Schedule. If this bit is a zero then the status of
the Asynchronous Schedule is disabled. If this bit is a one then the status of
the Asynchronous Schedule is enabled. The Host Controller is not required to
immediately disable or enable the Asynchronous Schedule when software
transitions the Asynchronous Schedule Enable bit in the USBCMD register.
When this bit and the Asynchronous Schedule Enable bit are the same value,
the Asynchronous Schedule is either enabled (1) or disabled (0).
status of the Asynchronous Schedule. If this bit is a zero then the status of
the Asynchronous Schedule is disabled. If this bit is a one then the status of
the Asynchronous Schedule is enabled. The Host Controller is not required to
immediately disable or enable the Asynchronous Schedule when software
transitions the Asynchronous Schedule Enable bit in the USBCMD register.
When this bit and the Asynchronous Schedule Enable bit are the same value,
the Asynchronous Schedule is either enabled (1) or disabled (0).
Power Well: Core
14
0b
RO
Periodic Schedule Status (PSS_0): This bit reports the current real status
of the Periodic Schedule. If this bit is a zero then the status of the Periodic
Schedule is disabled. If this bit is a one then the status of the Periodic
Schedule is enabled. The Host Controller is not required to immediately
disable or enable the Periodic Schedule when software transitions the
Periodic Schedule Enable bit in the USBCMD register. When this bit and the
Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0). The Prefetch-Based Pause feature
prevents this bit from transitioning to 0 if it currently has a request pending,
in addition to the regular Periodic DMA engine.
of the Periodic Schedule. If this bit is a zero then the status of the Periodic
Schedule is disabled. If this bit is a one then the status of the Periodic
Schedule is enabled. The Host Controller is not required to immediately
disable or enable the Periodic Schedule when software transitions the
Periodic Schedule Enable bit in the USBCMD register. When this bit and the
Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0). The Prefetch-Based Pause feature
prevents this bit from transitioning to 0 if it currently has a request pending,
in addition to the regular Periodic DMA engine.
Power Well: Core
13
0b
RO
Reclamation (RECL_0): This is a read-only status bit, which is used to
detect an empty asynchronous schedule. The operational model and valid
transitions for this bit are described in Section 4 of the EHCI Specification.
detect an empty asynchronous schedule. The operational model and valid
transitions for this bit are described in Section 4 of the EHCI Specification.
Power Well: Core