Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2378
Datasheet
12
1b
RO
HCHalted (HCHALT_0): This bit is a zero whenever the Run/Stop bit is a
one. The Host Controller sets this bit to 1 after it has stopped executing as a
result of the Run/Stop bit being set to 0, either by software or by the Host
Controller hardware (e.g. internal error). The Prefetch-Based Pause feature
prevents this bit from transitioning to 0 if it is currently has a request
pending, in addition to the regular DMA engines.
one. The Host Controller sets this bit to 1 after it has stopped executing as a
result of the Run/Stop bit being set to 0, either by software or by the Host
Controller hardware (e.g. internal error). The Prefetch-Based Pause feature
prevents this bit from transitioning to 0 if it is currently has a request
pending, in addition to the regular DMA engines.
Power Well: Core
11:6
000000b
RO
Reserved (RSVD): Reserved.
5
0b
RWC
Interrupt on Async Advance (IAA_0): System software can force the
host controller to issue an interrupt the next time the host controller
advances the asynchronous schedule by writing a one to the Interrupt on
Async Advance Doorbell bit in the USBCMD register. This status bit indicates
the assertion of that interrupt source.
host controller to issue an interrupt the next time the host controller
advances the asynchronous schedule by writing a one to the Interrupt on
Async Advance Doorbell bit in the USBCMD register. This status bit indicates
the assertion of that interrupt source.
Power Well: Core
4
0b
RWC
Host System Error (HSE_0): The Host Controller sets this bit to 1 when a
serious error occurs during a host system access involving the Host
Controller module. Memory read cycles initiated by the EHC that receive any
status other than Successful will result in this bit being set. When this error
occurs, the Host Controller clears the Run/Stop bit in the Command register
to prevent further execution of the scheduled TDs. A hardware interrupt is
generated to the system (if enabled in the Interrupt Enable Register).
serious error occurs during a host system access involving the Host
Controller module. Memory read cycles initiated by the EHC that receive any
status other than Successful will result in this bit being set. When this error
occurs, the Host Controller clears the Run/Stop bit in the Command register
to prevent further execution of the scheduled TDs. A hardware interrupt is
generated to the system (if enabled in the Interrupt Enable Register).
Power Well: Core
3
0b
RWC
Frame List Rollover (FLR_0): The Host Controller sets this bit to a one
when the Frame List Index (see Section 9.3.2.4) rolls over from its maximum
value to zero. Since the USB2 SIP only supports the 1024-entry Frame List
Size, the Frame List Index rolls over every time FRNUM[13] toggles.
when the Frame List Index (see Section 9.3.2.4) rolls over from its maximum
value to zero. Since the USB2 SIP only supports the 1024-entry Frame List
Size, the Frame List Index rolls over every time FRNUM[13] toggles.
Power Well: Core
2
0b
RWC
Port Change Detect (PCD_0): The Host Controller sets this bit to a one
when any port for which the Port Owner bit is set to zero has a change bit
transition from a zero to a one or a Force Port Resume bit transition from a
zero to a one as a result of a J-K transition detected on a suspended port.
This bit will also be set as a result of the Connect Status Change being set to
a one after system software has relinquished ownership of a connected port
by writing a zero to a port's Port Owner bit. This bit is allowed to be
maintained in the Auxiliary power well. Alternatively, it is also acceptable
that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with
the OR of all of the PORTSC change bits (including: Force port resume, over-
current change, enable/disable change and connect status change).
Regardless of the implementation, whenever this bit is readable (i.e., in the
D0 state), it must provide a valid view of the Port Status registers.
when any port for which the Port Owner bit is set to zero has a change bit
transition from a zero to a one or a Force Port Resume bit transition from a
zero to a one as a result of a J-K transition detected on a suspended port.
This bit will also be set as a result of the Connect Status Change being set to
a one after system software has relinquished ownership of a connected port
by writing a zero to a port's Port Owner bit. This bit is allowed to be
maintained in the Auxiliary power well. Alternatively, it is also acceptable
that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with
the OR of all of the PORTSC change bits (including: Force port resume, over-
current change, enable/disable change and connect status change).
Regardless of the implementation, whenever this bit is readable (i.e., in the
D0 state), it must provide a valid view of the Port Status registers.
Power Well: Core
Bit
Range
Default
& Access
Field Name (ID): Description