Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2379
18.9.6
USB2 Interrupt Enable (USB2INTR)—Offset 28h
Access Method
Default: 00000000h
1
0b
RWC
USB Error Interrupt (USBERRINT_0): The Host Controller sets this bit to
1 when completion of a USB transaction results in an error condition (e.g.,
error counter underflow). If the TD on which the error interrupt occurred also
had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification
for a list of the USB errors that will result in this interrupt being asserted.
1 when completion of a USB transaction results in an error condition (e.g.,
error counter underflow). If the TD on which the error interrupt occurred also
had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification
for a list of the USB errors that will result in this interrupt being asserted.
Power Well: Core
0
0b
RWC
USB Interrupt (USBINT_0): The Host Controller sets this bit to 1 on the
completion of a USB transaction, which results in the retirement of a Transfer
Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1
when a short packet is detected (actual number of bytes received was less
than the expected number of bytes).
completion of a USB transaction, which results in the retirement of a Transfer
Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1
when a short packet is detected (actual number of bytes received was less
than the expected number of bytes).
Power Well: Core
Bit
Range
Default
& Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
IAAE_0
HSEE_0
FL
RE_
0
PCIE_0
USB
E
IE_
0
USB
IE
_
0
Bit
Range
Default
& Access
Field Name (ID): Description
31:6
0000000h
RO
Reserved (RSVD): Reserved.
5
0b
RW
Interrupt on Async Advance Enable (IAAE_0): When this bit is a one,
and the Interrupt on Async Advance bit in the USBSTS register is a one, the
host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the Interrupt on Async
Advance bit.
and the Interrupt on Async Advance bit in the USBSTS register is a one, the
host controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the Interrupt on Async
Advance bit.
Power Well: Core