Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2381
18.9.8
Control Data Structure Segment Register
(CTRLDSSEGMENT)—Offset 30h
Access Method
Default: 00000000h
18.9.9
Periodic Frame List Base Address (PERIODICLISTBASE)—
Offset 34h
Access Method
Default: 00000000h
Bit
Range
Default
& Access
Field Name (ID): Description
31:14
000000000
000000000
b
RO
Reserved (RSVD): Reserved.
13:0
000000000
00000b
RW
Frame List Current Index/Frame Number (FLCIFN_0): The value in
this register increments at the end of each time frame (e.g. micro-frame).
Bits (12:3) are used for the Frame List current index. This means that each
location of the frame list is accessed 8 times (frames or micro-frames) before
moving to the next index
this register increments at the end of each time frame (e.g. micro-frame).
Bits (12:3) are used for the Frame List current index. This means that each
location of the frame list is accessed 8 times (frames or micro-frames) before
moving to the next index
Power Well: Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
UP
PA
D
DR_0
Bit
Range
Default
& Access
Field Name (ID): Description
31:0
00000000h
RW
Upper Address[63 (UPPADDR_0): 32]: This 32-bit field corresponds to
address bits 63:32 when forming a control data structure address.
address bits 63:32 when forming a control data structure address.
Power Well: Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h