Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2390
Datasheet
12
1b
RO
Port Power (PP_P0_0): Hard-wired with a value of '1' on the Intel EHC.
This indicates that the port does have power.
This indicates that the port does have power.
Power Well: Resume
11:10
00b
RO
Line Status (LS_P0_0): These bits reflect the current logical levels of the
D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of
low-speed USB devices prior to the port reset and enable sequence. This field
is valid only when the port enable bit is zero and the current connect status
bit is set to a one. The encoding of the bits are: Bits(11:10) USB State
Interpretation 00b SE0 Not Low-speed device, perform EHCI reset 10b J-
state Not Low-speed device, perform EHCI reset 01b K-state Low-speed
device, release ownership of port 11b Undefined Not Low-speed device,
perform EHCI reset
D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of
low-speed USB devices prior to the port reset and enable sequence. This field
is valid only when the port enable bit is zero and the current connect status
bit is set to a one. The encoding of the bits are: Bits(11:10) USB State
Interpretation 00b SE0 Not Low-speed device, perform EHCI reset 10b J-
state Not Low-speed device, perform EHCI reset 01b K-state Low-speed
device, release ownership of port 11b Undefined Not Low-speed device,
perform EHCI reset
Power Well: Resume
9
0b
RO
Reserved (RSVD): Reserved.
8
0b
RW
Port Reset (PORTRST_P0_0): 1=Port is in Reset. 0=Port is not in Reset.
Default = 0. When software writes a one to this bit (from a zero), the bus
reset sequence as defined in the USB Specification Revision 2.0 is started.
Software writes a zero to this bit to terminate the bus reset sequence.
Software must keep this bit at a one long enough to guarantee the reset
sequence, as specified in the USB Specification Revision 2.0, completes.
Note: when software writes this bit to a one, it must also write a zero to the
Port Enable bit. Note that when software writes a zero to this bit there may
be a delay before the bit status changes to a zero. The bit status will not read
as a zero until after the reset has completed. If the port is in high-speed
mode after reset is complete, the host controller will automatically enable
this port (e.g. set the Port Enable bit to a one). A host controller must
terminate the reset and stabilize the state of the port within 2 milliseconds of
software transitioning this bit from a one to a zero. For example: if the port
detets that the attached device is high-speed during reset, then the host
controller must have the port in the enabled state within 2ms of software
writing this bit to a zero. The HCHalted bit in the USB2STS register should be
a zero before software attempts to use this bit. The host controller may hold
Port Reset asserted to a one when the HCHALTED bit is a one. The Run/Stop
bit in the Command Register must be set in order for the Port Reset bit to be
cleared.
Default = 0. When software writes a one to this bit (from a zero), the bus
reset sequence as defined in the USB Specification Revision 2.0 is started.
Software writes a zero to this bit to terminate the bus reset sequence.
Software must keep this bit at a one long enough to guarantee the reset
sequence, as specified in the USB Specification Revision 2.0, completes.
Note: when software writes this bit to a one, it must also write a zero to the
Port Enable bit. Note that when software writes a zero to this bit there may
be a delay before the bit status changes to a zero. The bit status will not read
as a zero until after the reset has completed. If the port is in high-speed
mode after reset is complete, the host controller will automatically enable
this port (e.g. set the Port Enable bit to a one). A host controller must
terminate the reset and stabilize the state of the port within 2 milliseconds of
software transitioning this bit from a one to a zero. For example: if the port
detets that the attached device is high-speed during reset, then the host
controller must have the port in the enabled state within 2ms of software
writing this bit to a zero. The HCHalted bit in the USB2STS register should be
a zero before software attempts to use this bit. The host controller may hold
Port Reset asserted to a one when the HCHALTED bit is a one. The Run/Stop
bit in the Command Register must be set in order for the Port Reset bit to be
cleared.
Power Well: Resume
Bit
Range
Default
& Access
Field Name (ID): Description