Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2393
18.9.14 Port Status and Control (PORTSC3)—Offset 6Ch
Access Method
Default: 00003000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
WK
OCE_P0
_0
WK
D
S
CNN
T
E_
P
0
_
0
WK
CNN
T
E_
P
0
_
0
PT
C_P
0
_0
PIC_P
0
_0
PO
_P0
_
0
PP_P
0
_0
LS_P
0_0
RSVD
POR
T
R
S
T
_
P0
_0
SUSP_P
0_0
FP
R_
P
0
_
0
OCC_P0
_0
OCACT_P0
_0
PE
DC_P
0_0
RSVD
CSC_P0
_0
CCS_P0
_
0
Bit
Range
Default
& Access
Field Name (ID): Description
31:23
000h
RO
Reserved (RSVD): Reserved.
22
0b
RW
Wake on Over-current Enable (WKOCE_P0_0): Writing this bit to a one
enables the port to be sensitive to over-current conditions as wake-up
events. When enabled to do so, the EHC sets the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Over-
current Active bit (bit 4 of this register) is set.
enables the port to be sensitive to over-current conditions as wake-up
events. When enabled to do so, the EHC sets the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Over-
current Active bit (bit 4 of this register) is set.
Power Well: Resume
21
0b
RW
Wake on Disconnect Enable (WKDSCNNTE_P0_0): Writing this bit to a
one enables the port to be sensitive to device disconnects as wake-up
events. When enabled to do so, the EHC setsthe PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Current
Connect Status changes from connected to disconnected (i.e., bit 0 of this
register changes from 1 to 0).
one enables the port to be sensitive to device disconnects as wake-up
events. When enabled to do so, the EHC setsthe PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Current
Connect Status changes from connected to disconnected (i.e., bit 0 of this
register changes from 1 to 0).
Power Well: Resume
20
0b
RW
Wake on Connect Enable (WKCNNTE_P0_0): Writing this bit to a one
enables the port to be sensitive to device connects as wake-up events. When
enabled to do so, the EHC sets the PME Status bit in the Power Management
Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from disconnected to connected (i.e., bit 0 of this register changes
from 0 to 1).
enables the port to be sensitive to device connects as wake-up events. When
enabled to do so, the EHC sets the PME Status bit in the Power Management
Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from disconnected to connected (i.e., bit 0 of this register changes
from 0 to 1).
Power Well: Resume