Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2396
Datasheet
6
0b
RW
Force Port Resume (FPR_P0_0): 1= Resume detected/driven on port.
0=No resume (K-state) detected/driven on port. This functionality defined
for manipulating this bit depends on the value of the Suspend bit. For
example, if the port is not suspended (Suspend and Enabled bits are a one)
and software transitions this bit to a one, then the effects on the bus are
undefined. Software sets this bit to a 1 to drive resume signaling. The Host
Controller sets this bit to a 1 if a J-to-K transition is detected while the port is
in the Suspend state. When this bit transitions to a one because a J-to-K
transition is detected, the Port Change Detect bit in the USBSTS register is
also set to a one. If software sets this bit to a one, the host controller must
not set the Port Change Detect bit. Note that when the EHCI controller owns
the port, the resume sequence follows the defined sequence documented in
the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is
driven on the port as long as this bit remains a one. Software must
appropriately time the Resume and set this bit to a zero when the
appropriate amount of time has elapsed. Writing a zero (from one) causes
the port to return to high-speed mode (forcing the bus below the port into a
high-speed idle). This bit will remain a one until the port has switched to the
high-speed idle. The host controller must complete this transition within 2
milliseconds of software setting this bit to a zero.
0=No resume (K-state) detected/driven on port. This functionality defined
for manipulating this bit depends on the value of the Suspend bit. For
example, if the port is not suspended (Suspend and Enabled bits are a one)
and software transitions this bit to a one, then the effects on the bus are
undefined. Software sets this bit to a 1 to drive resume signaling. The Host
Controller sets this bit to a 1 if a J-to-K transition is detected while the port is
in the Suspend state. When this bit transitions to a one because a J-to-K
transition is detected, the Port Change Detect bit in the USBSTS register is
also set to a one. If software sets this bit to a one, the host controller must
not set the Port Change Detect bit. Note that when the EHCI controller owns
the port, the resume sequence follows the defined sequence documented in
the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is
driven on the port as long as this bit remains a one. Software must
appropriately time the Resume and set this bit to a zero when the
appropriate amount of time has elapsed. Writing a zero (from one) causes
the port to return to high-speed mode (forcing the bus below the port into a
high-speed idle). This bit will remain a one until the port has switched to the
high-speed idle. The host controller must complete this transition within 2
milliseconds of software setting this bit to a zero.
Power Well: Resume
5
0b
RWC
Over-current Change (OCC_P0_0): This bit gets set to a one when there
is a change to the Over-current Active bit. Software clears this bit by writing
a one to this bit position. The functionality of this bit is not dependent upon
the port owner.
is a change to the Over-current Active bit. Software clears this bit by writing
a one to this bit position. The functionality of this bit is not dependent upon
the port owner.
Power Well: Resume
4
0b
RO
Over-current Active (OCACT_P0_0): 1=This port currently has an over-
current condition. 0=This port does not have an over-current condition. This
bit will automatically transition from a one to a zero when the over current
condition is removed. The functionality of this bit is not dependent upon the
port owner. The Intel EHC automatically disables the port when the over-
current active bit is '1'.
current condition. 0=This port does not have an over-current condition. This
bit will automatically transition from a one to a zero when the over current
condition is removed. The functionality of this bit is not dependent upon the
port owner. The Intel EHC automatically disables the port when the over-
current active bit is '1'.
Power Well: Resume
3
0b
RWC
Port Enable/Disable Change (PEDC_P0_0): 1=Port enabled/disabled
status has changed. 0=No change. For the root hub, this bit gets set to a one
only when a port is disabled due to the appropriate conditions existing at the
EOF2 point (See Chapter 11 of the USB Specification for the definition of a
port error). This bit is not set due to the Disabled-to-Enabled transition, nor
due to a disconnect. Software clears this bit by writing a 1 to it.
status has changed. 0=No change. For the root hub, this bit gets set to a one
only when a port is disabled due to the appropriate conditions existing at the
EOF2 point (See Chapter 11 of the USB Specification for the definition of a
port error). This bit is not set due to the Disabled-to-Enabled transition, nor
due to a disconnect. Software clears this bit by writing a 1 to it.
Power Well: Resume
2
0b
RO
Reserved (RSVD): Reserved.
Bit
Range
Default
& Access
Field Name (ID): Description