Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
24
Datasheet
3.6
Chapter 1, “Introduction”
• Changed
Figure 1, “SoC Block Diagram” on page 148
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Chapter 1, “Terminology”
• Changed
Chapter 1, “Display Controller”
• Changed
Chapter 1, “Graphics and Media Engine”
• Changed
Chapter 1, “SKU List”
Chapter 2, “Physical Interfaces”
• Changed
Figure 3, “Signals (2 of 2)” on page 37
• Changed
Chapter 2, “Pin States Through Reset”
• Changed
Table 9, “USB 2.0 Device Interface Signals” on page 163
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Table 13, “Digital Display Interface Signals” on page 165
• Changed
Chapter 2, “PCU – iLB – Low Pin Count (LPC) Bridge Interface Signals”
• Changed
Table 24, “PCU - Serial Peripheral Interface (SPI) Signals” on page 172
• Changed
Table 30, “Power and Ground Pins” on page 180
Chapter 5, “Integrated Clock”
• Updated
Table 60, “SoC Clock Outputs” on page 277
Chapter 6, “Power Management”
• Updated
Table 118, “General Power States for System” on page 404
• Changed
Chapter 33, “Package C-States”
Chapter 7, “Power Up and Reset Sequence”
• Updated
Chapter 35, “G3 to S0”
• Updated
Table 129, “S4/S5 to S0 (Power Up) Sequence” on page 424
• Updated
Chapter 35, “S0 to S3 and S4/S5/G3 Sequence”
• Updated
Chapter 7, “S0 to S3 to S4/S5 (Power Down) Sequence without S0ix”
• Updated
Table 60, “S3/S4/S5 to S0 Cause of Wake Events” on page 104
• Updated
Chapter 7, “Reset Behavior”
Chapter 34, “Thermal Management”
• Updated
Chapter 34, “Thermal Management”
Chapter 9, “Electrical Specifications”
• Updated
Table 133, “Intel
®
Atom™ Processor E3800 Product Family Thermal
Specifications” on page 432
• Updated
Table 135, “Power Rail DC Specs and Max Current” on page 434
• Updated
Table 66, “VCC and VNN Currents” on page 115
• Updated
Table 72, “VGA_DDCCLK, VGA_DDCDATA Signal DC Specification” on page 126
• Updated
Table 146, “DDI DDC Signal DC Specification (DDI[1:0]_DDCDATA,
DDI[1:0]_DDCCLK)” on page 449
• Updated
Table 150, “PCI Express* DC Clock Request Input Signal Characteristics” on
page 451
• Updated
Table 83, “SD Card DC Specification” on page 131
• Updated
Table 84, “eMMC 4.5 Signal DC Electrical Specifications” on page 132
• Updated
Table 85, “TAP Signal Group DC Specification (TAP_TCK, TAP_TRSRT#,
TAP_TMS, TAP_TDI)” on page 133
• Updated
Table 86, “TAP Signal Group DC Specification (TAP_TDO)” on page 133
• Updated
Table 87, “TAP Signal Group DC Specification (TAP_PRDY#, TAP_PREQ#)” on
page 134
• Updated
Table 166, “Power Management & RTC Well Signal Group DC Specification
(PMC_RSMRST#, PMC_CORE_PWROK, ILB_RTC_RST#)” on page 463
• Updated
Table 167, “iLB RTC Well DC Specification (ILB_RTC_TEST#)” on page 463
• Added
Table 172, “GPIO 3.3V Suspend Well Signal Group DC Specification
(GPIO_S5[43:0])” on page 465
• Added
Table 172, “GPIO 3.3V Suspend Well Signal Group DC Specification
(GPIO_S5[43:0])” on page 465
• Updated
Table 103, “GPIO 1.8V Core Well Signal Group DC Specification
(GPIO_S0_SC[101:0])” on page 145
• Updated
Table 104, “GPIO 1.8V Suspend Well Signal Group DC Specification
(GPIO_S5[43:0])” on page 145
• Updated
Table 175, “I
2
C Signal Electrical Specifications” on page 466
January 2015
Revision
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Description
Revision Date