Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2415
18.9.19 Port Status and Control (PORTSC8)—Offset 80h
Access Method
Default: 00003000h
1
0b
RWC
Connect Status Change (CSC_P0_0): 1=Change in Current Connect
Status. 0=No change. Indicates a change has occurred in the port's Current
Connect Status. The host controller sets this bit for all changes to the port
device connect status, even if system software has not cleared an existing
connect status change. For example, the insertion status changes twice
before system software has cleared the changed condition, hub hardware will
be 'setting' an already-set bit (i.e., the bit will remain set). Software sets this
bit to 0 by writing a 1 to it.
Status. 0=No change. Indicates a change has occurred in the port's Current
Connect Status. The host controller sets this bit for all changes to the port
device connect status, even if system software has not cleared an existing
connect status change. For example, the insertion status changes twice
before system software has cleared the changed condition, hub hardware will
be 'setting' an already-set bit (i.e., the bit will remain set). Software sets this
bit to 0 by writing a 1 to it.
Power Well: Resume
0
0b
RO
Current Connect Status (CCS_P0_0): 1=Device is present on port. 0=No
device is present. This value reflects the current state of the port, and may
not correspond directly to the event that caused the Connect Status Change
bit (Bit 1) to be set.
device is present. This value reflects the current state of the port, and may
not correspond directly to the event that caused the Connect Status Change
bit (Bit 1) to be set.
Power Well: Resume
Bit
Range
Default
& Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
WK
OCE_P0_0
WKD
S
CN
NTE_P0_0
WKCN
NTE_P0_0
PT
C_P0_0
PIC_P0_0
PO_P0_0
PP_P0_0
LS_P0_0
RSVD
POR
T
RST_P0_0
SUSP_P0_0
FP
R
_
P0_0
OCC_P0_0
OCACT_P0_0
PEDC_P0_0
RSVD
CSC_P0_0
CCS_P0_0
Bit
Range
Default
& Access
Field Name (ID): Description
31:23
000h
RO
Reserved (RSVD): Reserved.
22
0b
RW
Wake on Over-current Enable (WKOCE_P0_0): Writing this bit to a one
enables the port to be sensitive to over-current conditions as wake-up
events. When enabled to do so, the EHC sets the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Over-
current Active bit (bit 4 of this register) is set.
enables the port to be sensitive to over-current conditions as wake-up
events. When enabled to do so, the EHC sets the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Over-
current Active bit (bit 4 of this register) is set.
Power Well: Resume