Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2420
Datasheet
18.9.20 Debug Port Control/Status Register (DP_CTRLSTS)—
Offset A0h
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 32 bits)
MBAR Reference:
[B:0, D:29, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
OW
N
E
R
C
NT
_0
RSVD
ENAB
LEDCNT
_0
RSVD
DONEST
S_
0
LINKIDST
S
_
0
RSVD
INUS
ECNT
_0
EXCP_ST
S
_0
ERR
G
OODST
S
_
0
GOCNT
_
0
WR
RDCN
T
_
0
DA
TA
LENCN
T
_
0
Bit
Range
Default
& Access
Field Name (ID): Description
31
0b
RO
Reserved (RSVD): Reserved.
30
0b
RW
OWNER_CNT (OWNERCNT_0): When software writes a 1 to this bit, the
ownership of the debug port is forced to the EHCI controller (i.e. immediately
taken away from the companion Classic USB Host Controller) If the port was
already owned by the EHCI controller, then setting this bit has no effect. This
bit overrides all of the ownership-related bits in the standard EHCI registers.
Note that the value in this bit does not affect the value reported in the
PORTSC Port Owner bit.
ownership of the debug port is forced to the EHCI controller (i.e. immediately
taken away from the companion Classic USB Host Controller) If the port was
already owned by the EHCI controller, then setting this bit has no effect. This
bit overrides all of the ownership-related bits in the standard EHCI registers.
Note that the value in this bit does not affect the value reported in the
PORTSC Port Owner bit.
Power Well: Core
29
0b
RO
Reserved (RSVD): Reserved.
28
0b
RW
ENABLED_CNT (ENABLEDCNT_0): This bit = 1 if the debug port is
enabled for operation. Software can clear this by writing a zero to it. The
hardware clears the bit for the same conditions where hardware clears the
Port Enable/Disable bit (in the PORTSC register). (Note this bit is not cleared
when software clears the Port Enabled/Disabled bit in the PORTSC.) Software
can directly set this bit if the port is already enabled in the associated Port
Status and Control register (this is enforced by the hardware). Reset default
= 0.
enabled for operation. Software can clear this by writing a zero to it. The
hardware clears the bit for the same conditions where hardware clears the
Port Enable/Disable bit (in the PORTSC register). (Note this bit is not cleared
when software clears the Port Enabled/Disabled bit in the PORTSC.) Software
can directly set this bit if the port is already enabled in the associated Port
Status and Control register (this is enforced by the hardware). Reset default
= 0.
Power Well: Core
27:17
000000000
00b
RO
Reserved (RSVD): Reserved.