Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2468
Datasheet
Default: 00960020h
19.6.2
HCSPARAMS1—Offset 4h
number of ports implemented is 2 because there is 1
DWC_USB2_HOST_NUM_U2_ROOT_PORTS and 1
DWC_USB3_HOST_NUM_U3_ROOT_PORT
Access Method
Default: 0200017Fh
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
HC
IVE
R
S
ION
RSVD
0
CA
PLE
N
GTH
Bit
Range
Default &
Access
Description
31:16
096h
RO
HCIVERSION:
This is a two-byte register containing a BCD encoding of the xHCI
specification revision number supported by this host controller. The most significant byte
of this register represents a major revision and the least significant byte is the minor
revision. e.g. 0100h corresponds to xHCI version 1.0.xs
15:8
0h
RO
RSVD0:
Reserved.
7:0
20h
RO
CAPLENGTH:
This register is used as an offset to add to register base to find the
beginning of the Operational Register Space.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
HCSPARAMS1:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1
MA
X
POR
T
S
H
C
S
PA
R
AMS1_RSV
D1
MAXINTRS
MAXSL
O
T
S
Bit
Range
Default &
Access
Description
31:24
02h
RO
MAXPORTS:
Number of Ports (MaxPorts). This field specifies the maximum Port
Number value, i.e. the highest numbered Port Register Set that are addressable in the
Operational Register Space (refer to Table 29). Valid values are in the range of 1h to
FFh. The value in this field shall reflect the maximum Port Number value assigned by an
xHCI Supported Protocol Capability, described in section 7.2. Software shall refer to
these capabilities to identify whether a specific Port Number is valid, and the protocol
supported by the associated Port Register Set.
23:19
0h
RO
HCSPARAMS1_RSVD1:
reserved