Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2473
19.6.8
Rsvd_HC—Offset 1Ch
reserved
Access Method
Default: 00000000h
19.6.9
USBCMD—Offset 20h
USB Command Register Bit Definitions
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Rsvd_HC:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
6
Bit
Range
Default &
Access
Description
31:0
0h
RO
RSVD6:
Reserved.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD8
EU3S
EW
E
CRS
CS
S
LH
CRS
T
RS
VD7
HS
EE
IN
T
E
HC
RST
R_S
Bit
Range
Default &
Access
Description
31:12
0h
RO
RSVD8:
reserved
11
0h
RW
EU3S:
Enable U3 MFINDEX Stop (EU3S) - RW. Default = 0. When set to 1, the xHC may
stop the MFINDEX counting action if all Root Hub ports are in the U3, Disconnected,
Disabled, or Powered-off state. When cleared to 0 the xHC may stop the MFINDEX
counting action if all Root Hub ports are in the Disconnected, Disabled, Training, or
Powered-off state. Refer to section 4.14.2 for more information.
10
0h
RW
EWE:
Enable Wrap Event (EWE) - RW. Default = 0. When set to 1, the xHC shall
generate a MFINDEX Wrap Event every time the MFINDEX register transitions from
03FFFh to 0. When cleared to 0 no MFINDEX Wrap Events are generated. Refer to
section 4.14.2 for more information. When this register is exposed by a Virtual Function
(VF), the generation of MFINDEX Wrap Events to VFs shall be emulated by the VMM.