Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2477
Default: 00000000h
19.6.13
CRCR_LO—Offset 38h
Register CRCR_LO
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
SVD13
N0_
N
15
Bit
Range
Default &
Access
Description
31:16
0h
RO
RSVD13:
reserved
15:0
0h
RW
N0_N15:
Reg field N0_N15
Type:
Memory Mapped I/O Register
(Size: 32 bits)
CRCR_LO:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CMD
_
RING_
PNTR
RSVD
14
CR
R
CA
CS
RCS
Bit
Range
Default &
Access
Description
31:6
0h
RW
CMD_RING_PNTR:
Command Ring Pointer - RW. Default = 0. This field defines high
order bits of the initial value of the 64-bit Command Ring Dequeue Pointer. Writes to this
field are ignored when Command Ring Running (CRR) = 1. If the CRCR is written while
the Command Ring is stopped (CCR = 0), the value of this field shall be used to fetch
the first Command TRB the next time the Host Controller Doorbell register is written
with the DB Reason field set to Host Controller Command. If the CRCR is not written
while the Command Ring is stopped (CCR = 0) then the Command Ring shall begin
fetching Command TRBs at the current value of the internal xHC Command Ring
Dequeue Pointer. Reading this field always returns 0.
5:4
0h
RO
RSVD14:
reserved