Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2480
Datasheet
19.6.17
CONFIG—Offset 58h
Configure Register Bit Definitions. This register is in the Aux Power well. It is only reset
by platform hardware during a cold reset or in response to a Host Controller Reset
(HCRST). The initial conditions of a port are described in section 4.19 of xhci
specification .
Access Method
Default: 00000000h
19.6.18
PORTSC1—Offset 420h
Access Method
Default: 000002A0h
Bit
Range
Default &
Access
Description
31:0
0h
RW
DEVICE_CONTEXT_BAAP:
Reg field DEVICE_CONTEXT_BAAP
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
17
MAXSL
O
T
S
E
N
Bit
Range
Default &
Access
Description
31:8
0h
RO
RSVD17:
reserved
7:0
0h
RW
MAXSLOTSEN:
Reg field MAXSLOTSEN
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PORTSC1:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0
WP
R
DR
RSVD
20
WOE
WDE
WC
E
RSVD
19
CE
C
PL
C
PRC
OC
C
WRC
PE
C
CS
C
LW
S
PIC
PO
R
T
S
PEED
PP
PLS
PR
OC
A
RSVD
18
PE
D
CC
S