Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2486

Datasheet

31

0h

RW

Warm Port Reset (WPR) RW1S/RsvdZ. Default = 0. When software writes a 1 to 

this bit, the Warm Reset sequence as defined in the USB3 Specification is initiated and 

the PR flag is set to 1. Once initiated, the PR, PRC, and WRC flags shall reflect the 

progress of the Warm Reset sequence. This flag shall always return 0 when read. Refer 

to section 4.19.5.1. This flag only applies to USB3 protocol ports. For USB2 protocol 

ports it shall be RsvdZ.

30

0h

RW

Device Removable (DR) - RO. This flag indicates if this port has a removable device 

attached. 1 = Device is non-removable. 0 = Device is removable.

29:28

0h

RO

reserved

27

0h

RW

Wake on Over-current Enable (WOE) RWS. Default = 0. Writing this bit to a 1 

enables the port to be sensitive to over-current conditions as system wake-up eventsn. 

Refer to section 4.15 for operational model.

26

0h

RW

Wake on Disconnect Enable (WDE) RWS. Default = 0. Writing this bit to a 1 

enables the port to be sensitive to device disconnects as system wake-up eventsn. Refer 

to section 4.15 for operational model.

25

0h

RW

Wake on Connect Enable (WCE) RWS. Default = 0. Writing this bit to a 1 enables 

the port to be sensitive to device connects as system wake-up events . Refer to section 

4.15 for operational model.

24

0h

RO

reserved

23

0h

RW

Port Config Error Change (CEC) RW1CS/RsvdZ. Default = 0. This flag indicates 

that the port failed to configure its link partner. 0 = No change. 1 = Port Config Error 

detected. Software shall clear this bit by writing a '1' to it. Refer to section 4.19.2 of 

XHCI specification for more information on change bit usage. Note: This flag is valid only 

for USB3 protocol ports. For USB2 protocol ports this bit shall be RsvdZ.

22

0h

RW

Port Link State Change (PLC) RW1CS. Default = 0. This flag is set to 1 due to the 

PLS transitions in the XHCI specification

21

0h

RW

Port Reset Change (PRC) RW1CS. Default = 0. This flag is set to 1 due to a '1' to 

'0' transition of Port Reset (PR). e.g. when any reset processing (Warm or Hot) on this 

port is complete. Note that this flag shall not be set to 1 if the reset processing was 

forced to terminate due to software clearing PP or PED to '0'. 0 = No change. 1 = Reset 

complete. Software shall clear this bit by writing a '1' to it. Refer to section 4.19.5.of 

XHCI specification. Refer to section 4.19.2 of XHCI specification. for more information 

on change bit usage.

20

0h

RW

Over-current Change (OCC) RW1CS. Default = 0. This bit shall be set to a 1 when 

there is a 0 to 1 or 1 to 0 transition of Over-current Active (OCA). Software shall clear 

this bit by writing a 1 to it. Refer to section 4.19.2 for more information on change bit 

usage.

19

0h

RW

Warm Port Reset Change (WRC) RW1CS/RsvdZ. Default = 0. This bit is set when 

Warm Reset processing on this port completes. 0 = No change. 1 = Warm Reset 

complete. Note that this flag shall not be set to 1 if the Warm Reset processing was 

forced to terminate due to software clearing PP or PED to '0'. Software shall clear this bit 

by writing a '1' to it. Refer to section 4.19.5.1. Refer to section 4.19.2 for more 

information on change bit usage. This bit only applies to USB3 protocol ports. For USB2 

protocol ports it shall be RsvdZ.

18

0h

RW

Port Enabled/Disabled Change (PEC) RW1CS. Default = 0. 1 = change in PED. 0 = 

No change. Note that this flag shall not be set if the PED transition was due to software 

setting PP to 0. Software shall clear this bit by writing a 1 to it. Refer to section 4.19.2 

for more information on change bit usage. For a USB2 protocol port, this bit shall be set 

to 1 only when the port is disabled due to the appropriate conditions existing at the 

EOF2 point (refer to section 11.8.1 of the USB2 Specification for the definition of a Port 

Error). For a USB3 protocol port, this bit shall never be set to 1.