Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2487
17
0h
RW
CSC: 
Connect Status Change (CSC) RW1CS. Default = 0. 1 = Change in CCS. 0 = No 
change. This flag indicates a change has occurred in the ports Current Connect Status 
(CCS) or Cold Attach Status (CAS) bits. Note that this flag shall not be set if the CCS 
transition was due to software setting PP to 0, or the CAS transition was due to software 
setting WPR to 1. The xHC sets this bit to 1 for all changes to the port device connect 
status , even if system software has not cleared an existing Connect Status Change. For 
example, the insertion status changes twice before system software has cleared the 
changed condition, root hub hardware will be setting an already-set bit (i.e., the bit will 
remain 1). Software shall clear this bit by writing a 1 to it. Refer to section 4.19.2 for 
more information on change bit usage.
16
0h
RW
LWS: 
Port Link State Write Strobe (LWS) RW. Default = 0. When this bit is set to 1 on a 
write reference to this register, this flag enables writes to the PLS field. When 0, write 
data in PLS field is ignored. Reads to this bit return 0.
15:14
0h
RW
PIC: 
Port Indicator Control (PIC) RWS. Default = 0. Writing to these bits has no effect if 
the Port Indicators (PIND) bit in the HCCPARAMS register is a 0
13:10
0h
RW
PORTSPEED: 
Port Speed (Port Speed) ROS. Default = 0. This field identifies the speed 
of the connected USB Device. This field is only relevant if a device is connected (CCS = 
1) in all other cases this field shall indicate Undefined Speed.
9
1h
RW
PP: 
Port Power (PP) RWS. Default = 1. This flag reflects a port's logical, power control 
state. Because host controllers can implement different methods of port power 
switching, this flag may or may not represent whether (VBus) power is actually applied 
to the port. When PP equals a '0' the port is nonfunctional and shall not report attaches, 
detaches, or Port Link State (PLS) changes. However, the port shall report over-current 
conditions when PP = 0 if PPC = 0. After modifying PP, software shall read PP and 
confirm that it is reached its target state before modifying it again , undefined behavior 
may occur if this procedure is not followed. 0 = This port is in the Powered-off state. 1 = 
This port is not in the Powered-off state. If the Port Power Control (PPC) flag in the 
HCCPARAMS register is '1', then xHC has port power control switches and this bit 
represents the current setting of the switch ('0' = off, '1' = on). If the Port Power Control 
(PPC) flag in the HCCPARAMS register is '0', then xHC does not have port power control 
switches and each port is hard wired to power, and not affected by this bit. When an 
over-current condition is detected on a powered port, the xHC shall transition the PP bit 
in each affected port from a 1 to 0 (removing power from the port). Note: If this is an 
SSIC Port, then the DSP Disconnect process is initiated by '1' to '0' transition of PP. Refer 
to section 5.1.2 in the SSIC Spec for more information. Refer to section 4.19.4 for more 
information.
8:5
5h
RW
PLS: 
Port Link State (PLS) RWS. Default = RxDetect (5). This field is used to power 
manage the port and reflects its current link state. When the port is in the Enabled 
state, system software may set the link U state by writing this field. System software 
may also write this field to force a Disabled to Disconnected state transition of the port.
4
0h
RW
PR: 
Port Reset (PR) RW1S. Default = 0. 1 = Port Reset signaling is asserted. 0 = Port is 
not in Reset. When software writes a 1 to this bit generating a 0 to 1 transition, the bus 
reset sequence is initiated ; USB2 protocol ports shall execute the bus reset sequence as 
defined in the USB2 Spec. USB3 protocol ports shall execute the Hot Reset sequence as 
defined in the USB3 Spec. PR remains set until reset signaling is completed by the root 
hub. Note that software shall write a 1 to this flag to transition a USB2 port from the 
Polling state to the Enabled state. Refer to sections 4.15.2.3 and 4.19.1.1. of XHCI 
specification. This flag is 0 if PP is 0.
3
0h
RW
OCA: 
Over-current Active (OCA) RO. Default = 0. 1 = This port currently has an over-
current condition. 0 = This port does not have an over-current condition. This bit shall 
automatically transition from a 1 to a 0 when the over-current condition is removed.
2
0h
RO
RSVD23: 
reserved
Bit 
Range
Default & 
Access
Description