Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2490
Datasheet
Access Method
Default: 00000000h
19.6.27
IMOD—Offset 464h
Interrupter Moderation Register. Software may use this register to pace (or even out)
the delivery of interrupts to the host CPU. This register provides a guaranteed inter-
interrupt delay between interrupts asserted by the xHC, regardless of USB traffic
conditions. To independently validate configuration settings, software may use the
following algorithm to convert the inter-interrupt Interval value to the common
'interrupts/sec' performance metric:
Access Method
Default: 00000FA0h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
IMAN:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD29
IE
IP
Bit
Range
Default &
Access
Description
31:2
0h
RO
RSVD29:
reserved
1
0h
RW
IE:
Interrupt Enable (IE) RW. Default = 0. This flag specifies whether the Interrupter is
capable of generating an interrupt. When this bit and the IP bit are set (1), the
Interrupter shall generate an interrupt when the Interrupter Moderation Counter
reaches 0. If this bit is 0, then the Interrupter is prohibited from generating interrupts.
0
0h
RW
IP:
Interrupt Pending (IP) - RW1C. Default = 0. This flag represents the current state of
the Interrupter. If IP = 1, an interrupt is pending for this Interrupter. A 0 value indicates
that no interrupt is pending for the Interrupter. Refer to section 4.17.5 of XHCI
specification for the conditions that modify the state of this flag.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
IMODC
IMODI
Bit
Range
Default &
Access
Description
31:16
0h
RW
IMODC:
Interrupt Moderation Counter (IMODC) - RW. Default = undefined. Down
counter. Loaded with the IMODI value whenever IP is cleared to '0', counts down to '0',
and stops. The associated interrupt shall be signaled whenever this counter is '0', the
Event Ring is not empty, the IE and IP flags = '1', and EHB = '0'. This counter may be
directly written by software at any time to alter the interrupt rate.