Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2491
19.6.28
ERSTSZ—Offset 468h
Event Ring Segment Table Size Register Bit Definitions.
Access Method
Default: 00000000h
19.6.29
RsvdP—Offset 46Ch
Access Method
Default: 00000000h
15:0
fa0h
RW
IMODI:
Interrupt Moderation Interval (IMODI) - RW. Default = '4000' (~1ms).
Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value
of '0' disables interrupt throttling logic and interrupts shall be generated immediately if
IP = '0', EHB = '0', and the Event Ring is not empty.
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ERSTSZ:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD30
E
R
S_T
A
BLE_SIZ
E
Bit
Range
Default &
Access
Description
31:16
0h
RO
RSVD30:
reserved
15:0
0h
RW
ERS_TABLE_SIZE:
Event Ring Segment Table Size RW. Default = 0. This field identifies
the number of valid Event Ring Segment Table entries in the Event Ring Segment Table
pointed to by the Event Ring Segment Table Base Address register. The maximum value
supported by an xHC implementation for this register is defined by the ERST Max field in
the HCSPARAMS2 register (5.3.4). For Secondary Interrupters: Writing a value of 0 to
this field disables the Event Ring. Any events targeted at this Event Ring when it is
disabled shall result in undefined behavior of the Event Ring. For the Primary
Interrupter: Writing a value of 0 to this field shall result in undefined behavior of the
Event Ring. The Primary Event Ring cannot be disabled.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h