Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2515

flag Value After Reset: 0x0 Register SUPTPRT3_DW0

Default: 03000002h

18

0h

RO

Integrated Hub Implementation (IHI) RO. Default = 1'b0. If this bit is cleared to 0, 

the Root Hub to External xHC port mapping adheres to the default mapping described in 

section 4.24.2.1. if this bit is set to 1, the Root Hub to External xHc port mapping does 

not adhere to the default mapping described in section 4.24.2.1, and an ACPI or other 

mechanism is required to define the mapping

17

0h

RO

High-speed Only (HSO) RO. Default = 1'b0. If this bit is cleared to 0 the USB2 

ports described by this capability are Low-, Full-, and high speed capable. If this bit is 

set to 1, the USB2 ports described by this capability are High-speed only, e.g. the ports 

dont support Low- or Full-Speed operation. High-speed only implementations may 

introduce a Teir mismatch, refer to section 4.24.2 for more information.

16

0h

RW

Reserved

15:8

0h

RW

Reg field COMPATIBLE_PORT_COUNT

7:0

01h

RW

Reg field COMPATIBLE_PORT_OFFSET

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

MA

JOR_REV

ISION

MINOR_REV

ISION

NEX

T

_CAP

ABILITY_

POI

N

T

E

R

CA

PA

BILITY

_ID

31:24

0x03

RW

0x0 Reg field MAJOR_REVISION

23:16

00h

RW

flag Value After Reset: 0x0 Reg field MINOR_REVISION

15:8

0h

RW

Reg field NEXT_CAPABILITY_POINTER

7:0

02h

RW

Reg field CAPABILITY_ID