Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2518

Datasheet

Global SoC Bus Configuration Register 1

Default: 00000F00h

4

0h

RW

INCR32 Burst Type Enable

3

0h

RW

INCR16 Burst Type Enable

2

1h

RW

INCR8 Burst Type Enable

1

1h

RW

INCR4 Burst Type Enable

0

0h

RW

Undefined Length INCR Burst Type Enable (INCRBrstEna). Input to 

BUS-GM When enabled, this has higher priority than other burst types. For the AHB 

configuration. if this bit is set to 1, AHB master tries to do only one INCR burst for each 

transfer unless it has to break it at a 1Kbyte boundary. If this bit is set to 0, the AHB 

master may still use INCR burst type at the beginning and end bursts of transfers to 

align the address. The middle bursts are INCR4/8/16, depending when the type is 

enabled.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

RS

VD0

EN1KP

A

G

E

BRE

Q

LIMIT

DA

TA

DRS

P

C

DES

A

DRS

P

C

31:13

0h

RO

reserved

12

0h

RW

1k Page Boundary Enable: By default (this bit is disabled) the AXI breaks 

transfers at the 4k page boundary. When this bit is enabled, the AXI master (DMA data) 

breaks transfers at the 1k page boundary.

11:8

fh

RW

AXI Pipelined Transfers Burst Request Limit (PipeTransLimit) The field 

controls the number of outstanding pipelined transfers requests the AXI master will 

push to the AXI slave. Once the AXI master reaches this limit, it will not make more 

requests on the AXI ARADDR and AWADDR buses until the associated data phases 

complete.This field is encoded as follows: h0: 1 request h1: 2 requests h2: 3 requests 

h3: 4 requests hF: 16 requests

7:4

0h

RW

Reserved

3:0

0h

RW

Reserved