Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2521
31
28
24
20
16
12
8
4
0
0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
PWRDNS
CA
LE
MAS
T
ER
FI
LT
B
Y
PASS
BYPS
S
E
TA
DDRINDEV
MODE
U2RS
TECN
FR
M
S
C
LD
W
N
PR
TC
AP
DIR
CORE
SOF
T
RST
SOFITP
S
Y
NC
G
C
T
L_RSVD
2
DE
BUGA
TT
AC
H
RA
MC
LK
SEL
SC
AL
E
D
OW
N
D
IS
S
CRA
M
BLE
G
C
T
L_RSVD
1
GB
LH
IB
ER
NA
T
IO
N
EN
DSB
LC
LKGTNG
Bit
Range
Default &
Access
Description
31:19
08b0h
RW
PWRDNSCALE:
Reg field PWRDNSCALE
18
0h
RW
MASTERFILTBYPASS:
Master Filter Bypass: When this bit is set to 1'b1, irrespective of
the parameter DWC_USB3_EN_BUS_FILTERS chosen, all the filters in the
DWC_usb3_filter module will be bypassed. The double synchronizers to mac_clk
preceding the filters will also be bypassed. For enabling the filters, this bit should be
1'b0.
17
0h
RW
BYPSSETADDRINDEVMODE:
16
0h
RW
U2RSTECN:
If the super speed connection fails during POLL or LMP exchange, the
device connects at non-SS mode. If this bit is set, then device attempts three more
times to connect at SS, even if it previously failed to operate in SS mode.
15:14
0h
RW
FRMSCLDWN:
This field scales down device view of a SOF/USOF/ITP duration. For SS/
HS mode: Value of 2'h3 implements interval to be 15. 625 us Value of 2'h2 implements
interval to be 31.25 us Value of 2'h1 implements interval to be 62.5 us Value of 2'h0
implements interval to be125us For FS mode, the scale-down value is multiplied by 8.
13:12
3h
RW
PRTCAPDIR:
Reg field PRTCAPDIR
11
0h
RW
CORESOFTRST:
Core Soft Reset (CoreSoftReset) 1b0 - No soft reset 1b1 - Soft reset to
core When you reset PHYs (using GUBS3PHYCFG or GUSB3PIPECTL registers), you must
keep the core in reset state until PHY clocks are stable. This controls the bus, ram, and
mac domain resets.
10
0h
RW
SOFITPSYNC:
Sync ITP to reference clock
9
0h
RO
GCTL_RSVD2:
Disable U1/U2 timer Scaledown (U1U2TimerScale) If set to '1' along
with GCTL[5:4] (ScaleDown) = 2'bX1 disables the scale down of U1/U2 inactive timer
values. This is for simulation mode only.
8
0h
RW
DEBUGATTACH:
Debug Attach
7:6
0h
RW
RAMCLKSEL:
Reg field RAMCLKSEL
5:4
0h
RW
SCALEDOWN:
reg field SCALEDOWN
3
0h
RW
DISSCRAMBLE:
Disable Scrambling
2
0h
RO
GCTL_RSVD1:
Reserved