Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2522
Datasheet
19.6.64
GSTS—Offset C118h
Global Status Register
Access Method
Default: 3E800002h
1
0h
RW
GBLHIBERNATIONEN:
This bit enables hibernation at the global level. If hibernation is
not enabled via this bit, the PMU immediately accepts the D0-)D3 and D3-)D0 power
state change requests, but does not save or restore any core state. In addition, the
PMUs will never drive the PHY interfaces and let the core continue to drive the PHY
interfaces.
0
0h
RW
DSBLCLKGTNG:
Disable Clock Gating
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
GSTS:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CBE
LT
R
SVD7
OTG
_
IP
BC_IP
AD
P_IP
Ho
st_IP
De
vice
_IP
CS
R
T
ime
out
BUSE
RRADD
RVLD
R6
CURMO
D
Bit
Range
Default &
Access
Description
31:20
3e8h
RO
CBELT:
Current BELT Value: In Host mode, this field indicates the minimum value of all
received device BELT values and the BELT value that is set by the Set Latency Tolerance
Value command.
19:11
0h
RO
RSVD7:
reserved
10
0h
RO
OTG_IP:
OTG Interrupt Pending: This field indicates that there is a pending interrupt
pertaining to OTG in OEVT register.
9
0h
RO
BC_IP:
Battery Charger Interrupt Pending: This field indicates that there is a pending
interrupt pertaining to BC in BCEVT register.
8
0h
RO
ADP_IP:
ADP Interrupt Pending: This field indicates that there is a pending interrupt
pertaining to ADP in ADPEVT register.
7
0h
RO
Host_IP:
Host Interrupt Pending: This field indicates that there is a pending interrupt
pertaining to xHC in the Host event queue.
6
0h
RO
Device_IP:
Device Interrupt Pending: This field indicates that there is a pending
interrupt pertaining to peripheral (device) operation in the Device event queue.
5
0h
RO
CSRTimeout:
CSR Timeout: When this bit is 1'b1, it indicates that software performed
a write or read to a core register that could not be completed within
DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: 65535).
4
0h
RO
BUSERRADDRVLD:
Bus Error Address Valid