Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2525

Register GBUSERRADDRLO

Default: 00000000h

31:22

1ffh

RW

 

21

0h

RW

 

20:18

0h

RW

 

17

0h

RW

Sparse Control Transaction Enable: Some devices are slow in 

responding to Control transfers. Scheduling multiple transactions in one microframe/

frame can cause these devices to misbehave. If this bit is set to 1'b1, the host controller 

schedules transactions for a Control transfer in different microframes/frames.

16

0h

RW

Reserving 85% Bandwidth for HS Periodic EPs

15

1h

RW

Compliance Mode for Device Address: When this bit is 1'b1, Slot ID may 

have different value than Device Address if max_slot_enabled ( 128. n 1'b1: Increment 

Device Address on each Address Device command. n 1'b0: Device Address is equal to 

Slot ID. The xHCI compliance requires this bit to be set to 1'. The 0' mode is for debug 

purpose only. This all ows you to easily identify a device connected to a port in the 

Lecroy or Eliisys trace during hardware debug. This bit is valid in Host and DRD 

configuration and is used in host mode operation only. Ignore this bit in device mode.

14

1h

RW

Host IN Auto Retry: When set, this field enables the Auto 

Retry feature. For IN transfers (non-isochronous) that encounter data packets with CRC 

errors or internal overrun scenarios, the auto retry feature causes the Host core to reply 

to the device with a non-terminating retry ACK (that is, an ACK transaction packet with 

Retry = 1 and NumP != 0). If the Auto Retry feature is disabled (default), the core will 

respond with a terminating retry ACK (that is, an ACK transaction packet with Retry = 1 

and NumP = 0). n 1'b0: Auto Retry Disabled n 1'b1: Auto Retry Enabled In device mode 

this bit should be 0

13:11

0h

RO

 

10:9

3h

RW

Device Timeout Coarse Tuning: This field is a Host mode parameter which 

determines how long the host waits for a response from device before considering a 

timeout. The core first checks the DTCT value. If it is 0, then the timeout value is 

defined by the DTFT. If it is non-zero, then it uses the following timeout values: n 2'b00: 

0 usec -) use DTFT value instead n 2'b01: 500 usec n 2'b10: 1.5 msec n 2'b11: 6.5 

msec

8:0

0h

RW

Device Timeout Fine Tuning: This field is a Host mode parameter which 

determines how long the host waits for a response from device before considering a 

timeout. For DTFT field to take effect, DTCT must be set to 2'b00. The DTFT value is the 

number of 125 MHz clocks * 256 to count before considering a device timeout. For the 

125 MHz clk (8 ns period), this is calculated as follows: (DTFT value) * 256 * (8 ns) 

Quick Reference: n if DTFT = 0x2, 2*256*8 = 4usec timeout n if DTFT = 0x5, 5*256*8 

= 10usec timeout n if DTFT = 0xA, 10*256*8 = 20usec timeout n if DTFT = 0x10, 

16*256*8 = 32usec timeout n if DTFT = 0x19, 25*256*8 = 51usec timeout n if DTFT = 

0x31, 49*256*8 = 100usec timeout n if DTFT = 0x62, 98*256*8 = 200usec timeout

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h