Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2537

High Speed port to bus instance mapping

Default: 00000000h

13:11

0h

RO

LTSSM PHY command State: n 000: PHY_IDLE (PHY command 

state is in IDLE. No PHY request pending) n 001: PHY_DET (Request to start Receiver 

detection) n 010: PHY_DET_3 (Wait for Phy_Status (Receiver detection)) n 011: 

PHY_PWR_DLY (Delay Pipe3_PowerDown P0 -) P1/P2/P3 request) n 100: PHY_PWR_A 

(Delay for internal logic) n 101: PHY_PWR_B (Wait for Phy_Status(Power state change 

request))

10:9

2h

RO

flag Value After Reset: 0x0 Reg field POWERDOWN

8

0h

RO

RxEq Train

7:6

1h

RO

flag Value After Reset: 0x0 Reg field TXDEEMPHASIS

5:3

0h

RO

LTSSM Clock State: n 000: CLK_NORM (PHY is in non-P3 state and 

PCLK is running) n 001: CLK_TO_P3 (P3 entry request to PHY) n 010: CLK_WAIT1 (Wait 

for Phy_Status (P3 request)) n 011: CLK_P3 (PHY is in P3 and PCLK is not running) n 

100: CLK_TO_P0 (P3 exit request to PHY) n 101: CLK_WAIT2 (Wait for Phy_Status (P3 

exit request))

2

0h

RO

Tx Swing

1

0h

RO

Rx Termination

0

0h

RO

Tx Ones/Zeros

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BINUM8

BINUM7

BINUM6

BINUM5

BINUM4

BINUM3

BINUM2

BINUM1

31:28

0h

RO

Reg field BINUM8

27:24

0h

RO

Reg field BINUM7

23:20

0h

RO

Reg field BINUM6