Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2544
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0
PH
YS
O
FTRS
T
GU
SB3PIP
E
C
T
L_RSVD
2
UX_EX
IT_IN_P
X
P
ING_ENHANCEMENT_EN
U1U2EXITF
A
IL_T
O_RECO
V
R
equestP1P2P3
S
tartRx
d
etU3RxDet
D
isRxDetU3RxDet
DELA
YP1P2P3
DELA
Y
P
0T
OP
1P2P3TRANS
SU
SP
ENDE
NABLE
D
A
TWID
TH
ABOR
TRXDE
T
U
2
EXIT
SK
IPRX
DET
LF
PS
P0
A
LG
N
P3P
2
TRA
N
O
K
P3
E
X
SI
G
P2
LFPSFIL
T
ER
GU
SB3PIP
E
C
T
L_RSVD
1
TX
_
S
W
IN
G
TX
_
M
A
R
GI
N
T
X
_
D
E_
EM
P
H
AS
IS
ELA
S
TIC_BU
FFE
R_MODE
Bit 
Range
Default & 
Access
Description
31
0h
RW
PHYSOFTRST: 
Reg field PHYSOFTRST
30:28
0h
RO
GUSB3PIPECTL_RSVD2: 
27
0h
RW
UX_EXIT_IN_PX: 
Ux Exit in Px: n 0: The core does U1/U2/U3 exit in PHY power state 
P0 (default behavior) n 1: The core does U1/U2/U3 exitin PHY power state P1/P2/P3 
respectively This bit is added for SS PHY workaround where SS PHY injects a glitch on 
pipe3_RxElecIdle while receiving Ux exit LFPS, and pipe3_PowerDown change is in 
progress. Note: This bit is used by third-party SS PHY. It should be set to '0' for 
Synopsys PHY.
26
0h
RW
PING_ENHANCEMENT_EN: 
Ping Enhancement Enable: When set, the Downstream 
port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS 
receive duration is 8 ns (one mac3_clk). This field is valid for Downstream port only. 
Note: This bit is used by third-party SS PHY. It should be set to '0' for Synopsys PHY.
25
1h
RW
U1U2EXITFAIL_TO_RECOV: 
Reg field u1u2exitfail_to_recov
24
0h
RW
REQUESTp1p2p3 (RequestP1P2P3): 
 
23
0h
RW
STARTRXDETU3RXDET (StartRxdetU3RxDet): 
Reg field StartRxDetU3RxDet
22
0h
RW
DISRXDETU3RXDET (DisRxDetU3RxDet): 
Disable Receiver Detection in U3/Rx.Det: 
When set, the core does not do receiver detection in U3 or Rx.Detect state. 
DWC_USB3_GUSB3PIPECTL_INIT[23] should be used to start receiver detection 
manually. This bit is valid for Downstream ports only. Delay P1P2P3 Delay P0 to P1/P2/
P3 request when entering U1/U2/U3 until (DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8) 
8B10B error occurs, or Pipe3_RxValid drops to 0. DWC_USB3_GUSB3PIPECTL_INIT[18] 
must be 1 to enable this functionality. Delay PHY power change from P0 to P1/P2/P3 
when link state changing from U0 to U1/U2/U3 respectively. n 1'b1: When entering U1/
U2/U3, delay the transition to P1/P2/P3 until the pipe3 signals, Pipe3_RxElecIlde is 1 
and pipe3_RxValid is 0 n 1'b0: When entering U1/U2/U3, transition to P1/P2/P3 without 
checking for Pipe3_RxElecIlde and pipe3_RxValid. Note: This bit should be set to '1' for 
Synopsys PHY. It is also used by third-party SS PHY.
21:19
0h
RW
DELAYP1P2P3: 
Reg field DelayP1P2P3
18
1h
RW
DELAYP0TOP1P2P3TRANS: 
 
17
0h
RW
SUSPENDENABLE: 
Reg field SUSPENDENABLE
16:15
0h
RO
DATWIDTH: 
Reg field DATWIDTH