Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2545

Default: 00000042h

14

1h

RW

 

13

0h

RW

Skip Rx Detect: When set, the core skips Rx Detection if pipe3_RxElecIdle 

is low. Skip is defined as waiting for the appropriate timeout, then repeating the 

operation.

12

0h

RW

LFPS P0 Align: When set, n The core deasserts LFPS transmission on the 

clock edge that it requests Phy power state 0 when exiting U1, U2, or U3 low power 

states. Otherwise, LFPS transmission is asserted one clock earlier. n The core requests 

symbol transmission two pipe3_rx_pclks periods after the PHY asserts PhyStatus as a 

result of the PHY switching from P1 or P2 state to P0 state. Currently, this bit is only 

used in USB 3.0 HUB with Synopsys PHY. For other USB 3.0 Host, Device, and DRD 

cores, this is not required.

11

0h

RW

Reg field P3P2TranOK

10

0h

RW

Reg field P3ExSigP2

9

0h

RW

Reg field LFPSFILTER

8:7

0h

RO

 

6

0h

RW

Reg field TX_SWING

5:3

0h

RW

Reg field TX_MARGIN

2:1

1h

RW

 

0

0h

RW

Reg field ELASTIC_BUFFER_MODE

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0

TXFS

TA

DD

R_0

TXFDE

P_0

31:16

0h

RW

Reserved.