Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
2561
19.6.119 DGCMDPAR—Offset C710h
Device Generic Command Parameter Register
Access Method
Default: 00000000h
Bit 
Range
Default & 
Access
Description
31:30
0h
RO
DSTS_RSVD2: 
 
29
0h
RO
DCNRD: 
Value After Reset: 0x1 Device Controller Not Ready: The bit indicates that the 
core is in the process of completing the state transitions after exiting from hibernation. 
Software must wait for this bit to be de-asserted to zero before processing DS 
TS.USBLnk
28
0h
RW
SRE: 
Save/Restore Error (SRE) -RW1C. Default = '0'. If an error occurs during a Save or 
Restore operation this bit shall be set to '1'. This bit shall be cleared to '0' when a Save 
or Restore operation is initiated or when written with '1'. Refer to section 4.23.2 for 
more information. When this register is exposed by a Virtual Function (VF), the VMM 
determines the state of this bit as a function of the Save/Restore completion status for 
the selected VF. Refer to section 8 for more information.x
27:26
0h
RO
DSTS_RSVD1: 
 
25
0h
RO
RSS: 
Restore State Status: This bit is similar to the USBSTS.RSS in host mode. When 
the controller has finished the save process, it will complete the command by setting 
DSTS.RSS to '0'
24
0h
RO
SSS: 
Save State Status: This bit is similar to the USBSTS.SSS in host mode. When the 
controller has finished the save process, it will complete the command by setting 
DSTS.SSS to '0'.
23
0h
RO
COREIDLE: 
flag Value After Reset: 0x1 Core Idle
22
0h
RO
DEVCTRLHLT: 
Device Controller Halted
21:18
4h
RO
USBLNKST: 
flag Value After Reset: 0x0 Reg field USBLNKST
17
1h
RO
RXFIFOEMPTY: 
RxFIFO Empty
16:3
0h
RO
SOFFN: 
Frame/Microframe Number of the Received SOF: When the core is operating at 
high-speed, this field contains a microframe number. When the core is operating at full- 
or low-speed, this field contains a frame number.
2:0
4h
RO
CONNECTSPD: 
Reg field CONNECTSPD
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
DGCMDPAR: 
BAR Type: 
PCI Configuration Register (Size: 32 bits)
BAR Reference: 
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PA
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