Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2636
Datasheet
19.6.254 OSTS—Offset CC10h
flag Value After Reset: 0x819 OTG Status Register
Access Method
Default: 00000019h
16
0h
RW
OTGADevSessEndDetEvntEn:
Session End Detected Event Enable
(OTGADevSessEndDetEvntEn) When this bit is set, OEVT.OTGADevSessEndEvnt is
enabled. Else the event is disabled
15:12
0h
RO
RSVD2:
reserved
11
0h
RW
OTGBDevBHostEndEvntEn:
B-device B-Host End Event Enable: When this bit is set,
OEVT.OTGBDevHostEndEvnt is enabled. If not, the event is disabled
10
0h
RW
OTGBDevHNPChngEvntEn:
B-Dev HNP Change Event Enable: When this bit is set,
OEVT.OTGBDevHNPChngEvnt is enabled. If not, the event is disabled
9
0h
RW
OTGBDevSessVldDetEvntEn:
Session Valid Detected Event Enable
(OTGBDevSessVldDetEvntEn) Set in B-device Mode Only: This Event is asserted when
there is a valid VBUS from A-device and B-device succeeds in starting a session.
8
0h
RW
OTGBDevVBUSChngEvntEn:
Vbus Change Event Enable: When this bit is set,
OEVT.OTGBDevVBUSChngEvnt is enabled. If not, the event is disabled
7:0
0h
RO
RSVD3:
reserved
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
OSTS:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
RSV
D
0
O
TGstate
RSV
D
1
xHC
IPrtP
ower
BSesVld
AS
es
V
ld
Co
nI
DSt
s
Bit
Range
Default &
Access
Description
31:12
0h
RO
RSVD0:
reserved
11:8
0h
RO
OTGstate:
This is a debug field indicating the current state of the OTG state machine.
Value Encoding 4'b0000 A_IDLE 4'b0001 A_WAIT_VRISE 4'b0010 A_WAIT_BCON
4'b0011 A_WAIT_VFALL 4'b0100 A_VBUS_ERR 4'b0101 A_HOST 4'b0110 A_SUSPEND
4'b1111 A_PERIPHERAL 4'b0111 A_WAIT_PPWR 4'b1000 B_IDLE 4'b1001 B_SRP_INIT
4'b1010 B_PERIPHERAL 4'b1011 B_WAIT_ACON 4'b1100 B_HOST 4'b1101
A_WAIT_SWITCH 4'b1110 B_WAIT _SWITCH
7:4
1h
RO
RSVD1:
reserved
3
1h
RO
xHCIPrtPower:
This bit reflects the PORTSC.PP bit in the xHCI register.