Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2638
Datasheet
Default: 00000000h
19.6.257 ADPEVT—Offset CC28h
ADP Event Register
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ADPCTL:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
En
aP
rb
EnaS
ns
AD
PE
n
AD
P
R
es
WB
RS
VD1
Bit
Range
Default &
Access
Description
31:29
0h
RO
RSVD0:
reserved
28
0h
RW
EnaPrb:
Enable Probe: When set to 1'b1 along with ADPEn, the core performs a probe
operation.
27
0h
RW
EnaSns:
ADP Enable: When set to 1'b1, the core performs either ADP probing or
sensing based on EnaPrb and EnaSns. ADPEn = 1'b0 gates the suspend clock for major
portion of ADP related logic.
26
0h
RW
ADPEn:
ADP Enable: When set to 1'b1, the core performs either ADP probing or sensing
based on EnaPrb and EnaSns. ADPEn = 1'b0 gates the suspend clock for major portion
of ADP related logic.
25
0h
RW
ADPRes:
ADP Reset: When set to 1'b1, the ADP controller is reset. This bit is auto-
cleared after the reset procedure is complete in the ADP controller.
24
0b
RO
WB:
Write Busy: n 1'b0: Write Completed n 1'b1: Write in Progress The application can
read or write ADPCFG and ADPCTL registers only if this field is cleared. Hardware sets
this bit when the write is in progress in the Suspend clock domain.
23:0
0h
RO
RSVD1:
reserved
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ADPEVT:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:22, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
Adp
PrbE
vnt
A
dpS
nsE
vnt
Adp
T
moutE
vnt
A
D
PRstCmp
ltEvn
t
RS
VD1
RT
IM