Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2639

ADP Event Enable Register

Default: 00000000h

31:29

0h

RO

Reserved

28

0h

RO

Write Behavior: oneToClear ADP Probe Event: When this event is set, it 

means that the Vbus voltage is greater than VadpPrb or VadpPrb is reached.

27

0h

RO

Write Behavior: oneToClear ADP Sense Event: When this event is set, it 

means that the Vbus voltage is greater than VadpSns or VadpSns is reached.

26

0h

RO

Write Behavior: oneToClear ADP Timeout Event: This event is relevant 

when ADP probe command is executed. When this event is set, it means that the ramp 

time is completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a 

debug feature that allows software to read the ramp time after each cycle.

25

0h

RO

Write Behavior: oneToClear This event, when set, indicates that the 

ADP Reset command is successful

24:11

0h

RO

reserved

10:0

0h

RO

RAMP TIME: These bits capture the latest time it took for Vbus to ramp from 

VADP_SINK to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows: 

n 0x000: 1 cycles n 0x001: 2 cycles n 0x002: 3 cycles and so on till, n 0x7FF: 2048 

cycles A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. Note for 

scaledown ramp_timeout, n PrbDelta = 2'b00 =) 6250 us n PrbDelta = 2'b01 =) 3125 

us n PrbDelta = 2'b10 =) 1562.5 us n PrbDelta = 2'b11 =) 781.25 us

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RS

VD0

Ad

pP

rb

EvntE

n

Adp

S

ns

EvntE

n

Ad

pTmou

tEvntE

n

ADPRs

tC

m

pl

tEvntE

n

RS

VD1

31:29

0h

RO

Reserved

28

0h

RW

ADP Probe Event Enable: When this bit is set, ADPPrbEvnt in ADPEVT 

register is enabled.

27

0h

RW

ADP Sense Event Enable: When this bit is set, AdpSnsEvntEn in 

ADPEVT register is enabled.